Kabushiki Kaisha Toshiba

Nec Corporation

Ntt Docomo, Inc.

Masashi Itoh

Yasuo Morinaga

Masaharu Nakatsuchi

Yutaka Matsumoto

Nobuaki Sasao

Satoshi Takase

Toshio Kaneda

Yukio Ozaki

Shuji Watanabe

The communication state information providing system comprises a cellular phone of an information provider, and an information providing device having an information receiving unit for receiving, via a wireless LAN, the communication state information transmitted from the cellular phone, a communication state information storage unit for storing the communication state information received by the information receiving unit associated with the phone number specifying the cellular phone, and an information transmitting unit for transmitting the communication state information stored in the communication state information storage unit to a destination associated with the phone number of the cellular phone.

Communication terminal, communication state information providing system, and method of providing communication state information

A current source circuit includes a series-circuit connected between a power source node and ground and comprising a reference current source circuit, a first transistor Q1 of an NPN type having its collector and base connected to each other and a second transistor Q2 having a multi-emitter area (N) and having a multi-emitter configuration. The current source circuit further includes a third transistor Q3 of an NPN type connected at its collector to the power source node, at its base to the base of the first transistor Q1 and at its emitter connected to the base of the second transistor and has an emitter area (M) and an input current source circuit connected between the emitter of the third transistor Q3 and ground to allow a flow of an input current Iin. The current source circuit still further includes a fourth transistor Q4 of an NPN type connected at its collector-to-emitter circuit between a current output node and the ground and at its base connected to the collector of the second transistor to allow a flow of an output current Iout. Relative to an input current Iin, the output current Iout is proportional to the reciprocal of a product (M.times.N) of emitter areas of the third transistor Q3 and second transistor Q2.

Current source circuit

A buffer circuit including current sources and switches to connect and disconnect current sources to an output node. The switches are controlled by voltage detectors for comparing an input signal with a reference level. When the reference level is a predetermined value, the amplitude of an output signal swings up to V.sub.CC and swings down to V.sub.EE.

Buffer circuit with wide dynamic range

Tuning detector

Disclosed is a pilot signal cancelling system employed in an FM stereo receiver which does not cause deterioration of the S-N ratio. The system includes an input terminal for inputting a composite signal; a level detector for verifying the level of a pilot signal; a low pass filter for smoothing an output of the level detector; a cancelling wave generating circuit fo producing a pilot cancelling signal in response to an output of the low pass filter; a lamp trigger circuit for inputting the output of the low pass filter and outputting a lamp trigger signal; a lamp drive circuit for inputting the lamp trigger signal; a first computing circuit, connected to the level detector, for differentiating between the pilot signal in the composite signal and the pilot cancelling signal produced in the cancelling wave generating circuit; a second computing circuit, connected to an output terminal, for differentiating between the composite signal and the pilot cancelling signal; the output terminal for outputting the result of second computing circuit; and a switching circuit for switching on and off the connection of the pilot cancelling signal to the second computing circuit, by synchronizing the switching with the lamp trigger signal.

Pilot signal cancelling system

A matrix circuit includes a first resistor having one end connected to receive a current signal and another end connected to a first output node, a second resistor having one end connected to the one end of said first resistor, a first bipolar transistor having a first collector connected to the another end of said second resistor, a first emitter connected to a circuit ground and a first base connected to said first collector, and a second bipolar transistor having a second collector connected to a second output node, a second emitter connected to said circuit ground and a second base connected to said first base.

Matrix circuit of FM stereo multiplex demodulation circuit

A buffer circuit comprises an interface node, a bipolar transistor having a collector connected to a first power source, an emitter connected to a second power source, and a base, for transferring a signal supplied to and from the interface node, and a diode structure formed between the emitter and base of the bipolar transistor, the diode structure containing a PN junction reversely coupled across the emitter-base junction of the bipolar transistor.

Buffer circuit with an electrostatic protector

A reactance control circuit comprising a variable reactance circuit whose reactance is determined by the currents flowing to first and second differential transistor circuits, a differential amplifier for producing first and second currents in accordance with an input voltage, and a DC amplifier circuit for amplifying the first and second currents and supplying the amplified currents to the variable reactance circuit in order to control the currents flowing to the first and second differential transistor circuits. The DC amplifier circuit includes first and second transistors for supplying output currents to the variable reactance circuit, and a base potential control circuit for, when the first and second currents are equal to each other, supplying a predetermined low potential to the bases of the first and second transistors so that the currents flowing to the first and second transistors are both reduced.

Reactance control circuit with a DC amplifier for minimizing a variation

A tone control circuit having a first differential amplifier and a second differential amplifier. The first differential amplifier comprises first and second transistors whose emitters are connected. The second differential amplifier comprises third and fourth transistors whose emitters are connected. The base and collector of the third transistor are connected to the base of the second transistor and the collector of the first transistor, respectively. The base and collector of the fourth transistor are connected to the base of the first transistor and the collector of the second transistor, respectively. A demodulated signal is input to the differential amplifier, and also to the second different amplifier via a band-pass filter. When a tone control signal is supplied to the bases of the first to fourth transistors, a signal generated by attenuating at least the low-frequency component of the demodulated signal is output from a tone control-signal output terminal connected to the collectors of the first to fourth transistors.

Tone controller for attenuating noise in the signal generated by

An output circuit built in a semiconductor integrated circuit having an output terminal comprises a first transistor having a base and a collector connected to the output terminal, a second transistor having a collector connected to a power source circuit, an input signal source connected to the emitters of the first and second transistors, and a DC amplifier circuit having an input end connected to the output terminal and an output end connected to the base of the second transistor, and operated according to a preset bias potential. A signal occurring at the output terminal is fed back to the base of the second transistor via the DC amplifier circuit.

Growing community of inventors

Yokohama, Japan

Masashi Itoh