Fuji Electric Co., Ltd.

Masashi Hoya

Naoyuki Kanai

Katsumi Taniguchi

The present invention is directed to provide a semiconductor module capable of achieving miniaturization and reduced manufacturing cost while suppressing surge voltage generated when switching the semiconductor elements. A semiconductor module includes a negative terminal and a positive terminal. The negative terminal has a negative fastening portion for fastening a negative polarity-side external terminal, a negative connection portion connected to a laminated substrate, and a negative intermediate portion arranged between the negative fastening portion and the negative connection portion. The positive terminal has a positive fastening portion for fastening a positive polarity-side external terminal, positive connection portions connected to the laminated substrate, and a positive intermediate portion facing the negative intermediate portion with a predetermined gap and arranged between the positive fastening portion and the positive connection portions.

Plurality of overlapping power terminals in a semiconductor module

Provided is a semiconductor device comprising a high-side switching device, a low-side switching device, a high-side driver configured to turn on/off the high-side switching device, a low-side driver configured to turn on/off the low-side switching device, a high-side driving external terminal configured to supply a power supply voltage for driving the high-side driver, and a protection circuit section connected to the high-side driving external terminal. The high-side driver may include a reference potential terminal set to a reference potential of the high-side driver. The protection circuit section may be connected between the high-side driving external terminal and the reference potential terminal.

Semiconductor device

A semiconductor unit includes transistor chips; first main circuit terminals that are electrically connected to first main electrodes of the transistor chips; second main circuit terminals that are electrically connected to second main electrodes of the transistor chips; and a sealing body that has two sides and positioned on opposite sides from one another in one direction and that seals the transistor chip and the first and second main circuit terminals except for a portion of each of the first and second main circuit terminals. Moreover, the first main circuit terminals are respectively arranged in both corners of the one side and in a center of the other side of the two sides of the sealing body, and the second main circuit terminals are respectively arranged in a center of the one side and in both corners of the other side of the sealing body.

Semiconductor unit, semiconductor module, and semiconductor device

A manufacturing method of a semiconductor module including a trimming resistance element and a plurality of transistor chips connected mutually in parallel, in which gate electrodes are connected to one end of the trimming resistance element, including: measuring elapsed time and a gate-source voltage value when a predetermined gate current is injected into the gate electrodes and a predetermined drain current flow; calculating a gate-source capacity on the basis of the gate-source voltage value; determining a compensation gate resistance value on the basis of the gate-source voltage value and the gate-source capacity; and changing a resistance value of the trimming resistance element such that the resistance value of the trimming resistance element is conformed to the compensation gate resistance value.

Manufacturing method of semiconductor module

A semiconductor unit includes: a plurality of transistor chips arranged in a plurality of parallel rows, each transistor chip respectively having a first main electrode on one surface and a second main electrode on another surface; a first conductor layer electrically connected to the first main electrodes of the transistor chips, both corner portions on one end of the first conductor layer being drawn out in a direction in which the rows of transistor chips run; a second conductor layer arranged between the both corner portions of the first conductor layer; and a wiring substrate that is arranged on a side of the second main electrodes of the plurality of transistor chips and includes a wiring layer electrically connected to the second main electrodes of the plurality of transistor chips and to the second conductor layer.

Growing community of inventors

Nagano, Japan

Masashi Hoya