Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi Device Engineering Co., Ltd.

Hitachi Vlsi Engineering Corp.

Other

Elpida Memory, Inc.

Fuji Photo Film Company, Limited

Hitachi Ulsi Systems Co., Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Tohbu Semiconductor, Ltd.

Tessera Advanced Technologies, Inc.

Rising Silicon, Inc.

Hitachi Vsli Engineering Corp.

Vlsi Engineering Corporation

Masashi Horiguchi

Kiyoo Itoh

Masakazu Aoki

Takeshi Sakata

Kazuhiko Kajigaya

Yoshinobu Nakagome

Jun Etoh

Ryoichi Hori

Shinichi Ikenaga

Takayuki Kawahara

Mitsuru Hiraki

Kunio Uchiyama

Kazuyoshi Oshima

Yasuhiro Kasama

Manabu Tsunozaki

Akira Endo

Takashi Yamazaki

Kazuyuki Miyazawa

Takesada Akiba

Yuji Sakai

Hiroshi Yoshioka

Yasunori Yamaguchi

Tetsurou Matsumoto

Makoto Morino

Shinji Udo

Eiji Miyamoto

Mitsuhiro Takano

Sinichi Miyatake

Jiro Sawada

Hirokazu Saito

Atsushi Kumata

Hitoshi Tanaka

Masayuki Nakamura

Yasushi Kawase

Ken Shibata

Hiroki Miyashita

Sadayuki Ohkuma

Binhaku Taruishi

Hiromasa Noda

Osamu Nagashima

Youji Idei

Masaharu Kubo

Hideharu Yahata

Toshikazu Tachibana

Shigeki Ueda

Hiroyuki Mizuno

Asao Nishimura

Nozomu Matsuzaki

Kazuyoshi Shiba

Takayasu Ito

Toshio Miyamoto

Koki Noguchi

Shinya Sano

Satoshi Michishita

Yoshikazu Saitoh

Goro Kitsukawa

Katsuhiro Shimohigashi

Yoshiki Kawajiri

Osamu Ozawa

Ryoichi Kurihara

Takahiro Miki

Toshio Sasaki

Yuichi Okuda

Yasuhiko Takahashi

Kan Takeuchi

Katsumi Matsuno

Kiyoshi Inoue

Hiroki Fujisawa

Norio Hasegawa

Kazumasa Yanagisawa

Yoji Nishio

Hideki Osaka

Toshio Sugano

Tsugio Takahashi

Yoshitaka Tadaki

Seiji Funaba

Makoto Ohkura

Aritoshi Sugimoto

Toshiaki Masuhara

Osamu Minato

Setsuji Tatsumi

Shinichi Fukada

Susumu Hatano

Kazuya Ito

Makoto Ogasawara

Seiichiro Tsukui

Kiyonori Ohyu

Katsumi Otake

Tadashi Kameyama

Toyohiko Komatsu

Takao Watanabe

Hideo Nakamura

Shinichi Miyatake

Yuji Yatsuda

Tetsuro Matsumoto

Hiroshi Kawamoto

Tetsu Udagawa

Katsuaki Takagi

Naoya Arisaka

Kyoko Ishii

A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q, Q) having emitter terminals at the same electric potential. A base terminal of Qis disposed on a collector side of Q. A first resistance element connects the collector side of Qwith the base side of Q; and a second resistance element (R) connects a collector side of Qto R. A third resistance element (R) connects a base terminal of Qwith the electric potential of the emitter terminals. An amplifier (A) outputs a voltage based on a voltage difference between the collector sides of Qand Q; and a voltage-current converting section (MP, MP) converts amplifier output into a current supplied to the connection node of Rand R. A voltage is then output on the basis of the generated current.

Voltage generating circuit

The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.

Semiconductor device having voltage generation circuit

A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.

Crystal oscillation device and semiconductor device

A semiconductor device with improved temperature detection accuracy includes a coefficient calculation circuitry which calculates a plurality of N-th order coefficients, where N is an integer equal to or greater than one, of a correction function as an N-th order approximation of a characteristic function which relates temperature data measured by the temperature sensor and the actual temperature. The coefficient calculation circuitry uses N+1 pieces of the temperature data including a theoretical value at absolute zero in the characteristic function and N measured values of the temperature data measured by the temperature sensor unit at N points of temperature. A corrected temperatures are output using the correction function with the calculated coefficients and measured temperature values.

Semiconductor device and data generation method

The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

Method of forming a CMOS structure having gate insulation films of different thicknesses

The present invention provides a semiconductor device including a first terminal and a second terminal respectively coupled to both ends of a crystal resonator, an inverter circuit having an input coupled to the first terminal and an output coupled to the second terminal, a feedback resistor which couples between the first terminal and the second terminal, a variable capacitor coupled to at least one of the first and second terminals, and a control circuit. The control circuit performs control to increase both of the drive capability of the inverter circuit and the capacitance value of the variable capacitor in a second mode rather than a first mode.

Semiconductor device and control method thereof

A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.

Semiconductor integrated circuit device

A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.

Semiconductor device

Growing community of inventors

Kawasaki, Japan

Masashi Horiguchi