Texas Instruments Corporation

Other

Masashi Hashimoto

Gene A Frantz

John Victor Moravec

Jean-Pierre Dolait

Oh-Kyong Kwon

Satwinder S Malhi

Masaaki Aoki

Kaoru Awaka

Anjana Ghosh

Shivaling S Mahant-Shetti

Atsushi Yokoyama

Thomas J Aton

James Norman Hall

Takeshi Ishii

Shigeyoshi Arai

Thirumalai Sridhar

Eng C Born

Shivaling S Mahant-Shitti

Jean P Dolait

On-Kyong Kwon

Akio Ohya

Takemasa Shibata

Hironori Ohba

A memory circuit () having features specifically adapted to permit the memory circuit () to serve as a video frame memory is disclosed. The memory circuit () contains a dynamic random access memory array () with buffers () on input and output data ports () thereof to permit asynchronous read, write and refresh accesses to the memory array (). The memory circuit () is accessed both serially and randomly. An address generator () contains an address buffer register () which stores a random access address and an address sequencer () which provides a stream of addresses to the memory array (). An initial address for the stream of addresses is the random access address stored in the address buffer register ().

SDRAM with command decoder coupled to address registers

SDRAM with command decoder, address registers, multiplexer, and sequencer

A method for laser-assisted separation and enrichment of silicon isotopes such as Si, Si and Si on the basis of infrared multiple-photon dissociation of silicon halides represented by Si F , wherein the silicon halides are irradiated synchronously with multiple infrared pulsed laser beams at different wavelengths.

Method for efficient laser isotope separation and enrichment of silicon

A memory circuit ( ) having features specifically adapted to permit the memory circuit ( ) to serve as a video frame memory is disclosed. The memory circuit ( ) contains a dynamic random access memory array ( ) with buffers ( ) on input and output data ports ( ) thereof to permit asynchronous read, write and refresh accesses to the memory array ( ). The memory circuit ( ) is accessed both serially and randomly. An address generator ( ) contains an address buffer register ( ) which stores a random access address and an address sequencer ( ) which provides a stream of addresses to the memory array ( ). An initial address for the stream of addresses is the random access address stored in the address buffer register ( ).

Process of operating a DRAM system

Synchronous DRAM with control data buffer

Process of using a DRAM with address control data

Synchronous data system with control data buffer

Memory device for transferring streams of data

Process for controlling reading data from a DRAM array

System with control data buffer for transferring streams of data

Synchronous DRAM system with control data

A memory circuit ( ) having features specifically adapted to permit the memory circuit ( ) to serve as a video frame memory is disclosed. The memory circuit ( ) contains a dynamic random access memory array ( ) with buffers ( ) on input and output data ports ( ) thereof to permit asynchronous read, write and refresh accesses to the memory array ( ). The memory circuit ( ) is accessed both serially and randomly. An address generator ( ) contains an address buffer register ( ) which stores a random access address and an address sequencer ( ) which provides a stream of addresses to the memory array ( ). An initial address for the stream of the addresses is the random access address stored in the address buffer register ( ).

Synchronous data transfer system

Synchronous DRAM System with control data

A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diode coupled with a capacitor.

Method of fabricating electrically isolated double gated transistor

Synchronous DRAM device having a control data buffer

Growing community of inventors

Garland, TX, United States of America

Masashi Hashimoto