Fujitsu Corporation

Masashi Asakawa

Noriyuki Matsui

Yasuo Kousaki

Tendo Hirai

Shigeru Takamura

A data readout circuit of memory cells for reading out data from the memory cells includes a determination circuit () that reads out a plurality of data from multiplexed memory cells () having a unique data inversion direction and determines data not inverted in the data inversion direction as valid data stored in the memory cells () in a case when there are different data in the readout data; and an output unit () that outputs the data determined as valid data by the determination circuit () as memory data of the memory cells.

Data readout circuit of memory cells, memory circuit and method of reading out data from memory cells

Includes the information search database as a knowledge database storing a plurality of causes, a plurality of questions having the cause-and-effect relation with the plurality of causes, and correlation levels showing a degree of the correlations between the causes and corresponding questions. The search control unit extracts certain questions out of the plurality of questions by the algorithm based on the correlation levels and extracting causes with high correlation levels out of the plurality of causes based on the searcher's answer result to each of the certain questions from the information database, and then presenting the causes thus extracted as the search result.

Method of and computer program for searching information

A memory array is divided into a plurality of blocks. A plurality of mode storage units is so disposed as to correspond to the memory blocks. When a plurality of controllers outputs a mode setting instruction at the time of making of power, a setting unitsets control information designated by the mode setting instruction to the corresponding mode storage unit. When different controllers gain access to a synchronous DRAM, an access operation is executed for the corresponding memory block in accordance with the control information.

Synchronous DRAM utilizable as shared memory

A circuit that prevents illegal transformation of data in a non-volatile memory comprises a three circuits which generate three reference currents of different amplitude, there comparison circuits which respectively compare the three reference currents with a cell current, a writing/deletion circuit which writes data in or deletes data from the cells. A control circuit is provided which outputs a corresponding information based on the result of comparison by the comparison circuit, and makes said writing/deletion circuit execute writing data in or deletion of data from a target cell once more when the cell current is greater than the second reference current or the cell current is not greater than the third reference current.

Growing community of inventors

Kawasaki, Japan

Masashi Asakawa