Sanyo Electric Co., Ltd.

Daikin Industries, Ltd.

Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

Tokyo Sanyo Electric Co.

Masashi Arai

Kanji Tanaka

Tsutomu Ishikawa

Ryuichi Ogawa

Kazuhisa Ishiguro

Noboru Usui

Hiroki Seyama

Takashi Shibanuma

Daisuke Karube

Takahiro Kawashima

Takehiro Chaki

Akira Tsukihashi

Hiroshi Inoguchi

Satoru Sekiguchi

Hiroshi Kojima

Masami Nishiumi

Hisayoshi Uchiyama

Toshiyuki Take

Masaaki Nara

Hiroshi Kobori

Kiyoshi Takada

Rui Kurihara

Hideo Kunii

This invention provides a process for producing a fluoroolefin comprising reacting, in a vapor phase, a fluorinating agent and a chlorine-containing alkene or a chlorine-containing alkane in the presence of at least one catalyst selected from the group consisting of chromium oxide containing a Group 5 element and fluorinated chromium oxide containing a Group 5 element. According to the process of the present invention, the target fluoroolefin can be obtained with high starting material conversion and good selectivity.

Process for producing fluorine-containing olefin

An optical-pickup apparatus includes: a first laser light source including a first laser diode to emit a laser beam having a first wavelength, and a back-monitor photodetector to receive the laser beam emitted in a backward direction, not being an optical-disc direction, and output a first monitor signal; a second laser-light source including a second laser diode to emit a laser beam having a second wavelength; a light-receiving circuit including a front-monitor photodetector to receive the laser beam emitted in a forward direction, being the optical-disc direction, and output a second monitor signal, and a switch circuit to be inputted with the first and second monitor signals, and output the first or second monitor signal according to a switch signal; and first and second drive circuits to drive the first and second laser diodes according to the first and second monitor signals outputted from the light-receiving circuit, respectively.

Optical pickup apparatus, integrated circuit, and method for controlling laser output of optical pickup apparatus

An integrated circuit for optical disc comprising for each of light-receiving surfaces: an operational amplifier including inverting and noninverting input terminals receiving first and second input voltages, and output terminal receiving output voltage; a feedback resistor connected between the inverting input and output terminals; a photodiode connected between one power supply line of the first and second power supply lines and the inverting input terminal to generate current corresponding to reflected light; a capacitor connected between the one power supply line and the noninverting input terminal; and an input resistor connected between reference power source and the noninverting input terminal, further comprising: an adder adding voltages corresponding to the output voltages to generate RF signal, capacitance of the capacitor and resistance value of the input resistor being determined in accordance with capacitance of parasitic capacitor connected in parallel with the photodiode and resistance value of the feedback resistor.

Integrated circuit for optical disc

A mold,for molding semiconductor chips,and,serving as a light emitting element and a light receiving element, respectively, is made of a material capable of transmitting light. A groove,is formed on the region where light is emitted from and incident on the semiconductor chips so that it constitutes a reflecting face. Thus, the light is emitted and incident through the side E of the mold. In this configuration, the outer size of the light receiving element or light emitting element can be minimized, and the module provided with these semiconductor chips can also be miniaturized.

Optical semiconductor device and optical semiconductor module equipped with the same

A current to voltage conversion circuit is formed of a differential amplifier circuit (1) with a negative input terminal connected to a light receiving element (3) and a register (4) which feeds back an output signal to the negative input terminal of the differential amplifier circuit (1) thereof. The variable gain amplifier circuit (5) amplifies the output voltage of the current to voltage conversion circuit to detect the bottom value of the output signal thereof. The comparator circuit (7) compares the bottom value with the reference value Vr1 so that current flowing through the resistor (4) can be adjusted according to the difference between the bottom value and the reference value Vr1. The offset of the output signal from the variable gain amplifier circuit (5) supplied through the output terminal OUT is thereby adjusted. Since the peak value of the output signal of the variable gain amplifier circuit (5) is detected and the gain of the variable gain amplifier circuit (5) is controlled according to the difference between the peak value and the reference value Vr2, an output signal of a predetermined level can be obtained.

Offset correction circuit

An error signal generating circuit for adjusting a position of a sub-beam on an optical disc to a correct one. A timing circuit generates a test signal so that a driver drives a tracking coil. As a result, a difference signal is generated in a difference signal generating circuit and is then compared to a reference value in a comparing circuit. A controlling signal is generated in a controlling circuit in reply to a comparing error so as to be held in a holding circuit. The thus held controlling signal is converted into an analog signal in a D/A converter and is then applied to a VCA to vary the amplifying rate, such that the difference signal becomes zero when a correct tracking operation is being carried out.

Error correcting apparatus with error corecting signal holding function

A variable gain amplifier includes a first stage amplifying portion and a subsequent stage amplifying portion for amplifying an output from the first stage amplifying portion and outputting an amplified signal to an output terminal. The first stage amplifying portion includes first and second transistors having emitters connected to each other through a resistor based upon which an input dynamic range is determined, and first and second diodes which are connected to collectors of the transistors as loads thereof. A reference current is generated by a reference current generating portion. A control current generating portion generates a control current which is N times the reference current and supplied to the collectors of the first and second transistors. Currents flowing through the first and second diodes is sunk by a current sinking portion. Values of the above reference current and a sunk current by the current sinking portion is controlled by a control portion in accordance with a level of a control signal, whereby a total gain of the variable amplifier can be varied.

Variable gain amplifier

A PLL circuit comprises a variable frequency divider (7) for frequency-dividing a signal having a reference frequency f.sub.1 with a frequency dividing ratio n.sub.1 or n.sub.2, a fixed frequency divider (8) for further frequency-dividing an output of the variable frequency divider with a frequency dividing ratio n.sub.0, to generate a first output signal and a second output signal which is out of phase by 90.degree. from the first output signal, multiplier (10) for multiplying an input signal by the second output signal, a comparator (11) for comparing an output of the multiplier with a predetermined reference voltage, and a D-type flip-flop (12) receiving as a D input an output of the comparator and receiving as a clock input the first output signal, an output of the D-type flip-flop (12) being applied to the variable frequency divider (7). When the second output signal leads the input signal by 90.degree. or more, the output of the D-type flip-flop (12) attains an 'L' level, so that the large frequency dividing ratio n.sub.2 is selected. On the other hand, when the second output signal lags the input signal by 90.degree. or more, the output of the D-type flip-flop (12) attains an 'H' level, so that the small frequency dividing ratio n.sub.1 is selected.

PLL circuit for generating output signal synchronized with input signal

An improved FMX sterophonic broadcast receiver provided with countermeasures against transient noises, which includes a level detection circuit for detecting level of a detected stereo difference signal, and a level control circuit for controlling level of an expanded stereo difference signal according to an output signal of the level detection circuit. By the above arrangement of the present invention, since it is so arranged to cause the level control circuit to function when the degree of modulation becomes large so as to control the level of the stereo difference signal to be low, a level difference is produced between the stereo sum signal and the stereo difference signal for deterioration of the stereo separation degree upon matrixing at a matrix circuit for reduction of noises accordingly.

FMX stereophonic broadcast receiver

An FMX stereophonic receiver receives an FMX stereophonic broadcast signal which includes a stereo sum signal, an uncompressed stereo difference signal, and a compressed stereo difference signal which is formed by modulating the uncompressed stereo difference signal by a quadrature modulation and being compressed. The FMX stereophonic receiver includes an FM detector for producing an FM detection signal including a stereo pilot signal, a PLL circuit for producing a signal which is in a synchronized relationship with the stereo pilot signal included in the FM detection signal, a synchronous detection circuit for receiving the FM detection signal and for producing the uncompressed stereo difference signal in accordance with the signal produced from the PLL circuit, a quadrature detection circuit for receiving the FM detection signal and for producing the compressed stereo difference signal in accordance with the signal produced from the PLL circuit, and a phase shifting means for shifting the phase of at least one of the FM detection signal applied to the PLL circuit and the FM detection signal applied to the detection circuits so as to correct the phase difference between the synchronous detection signal and the signal to be detected.

FMX stereophonic receiver

An FM/FMX stereophonic receiver is capable of receiving an FM or an FMX stereophonic broadcast signal. The FM stereophonic broadcast signal includes a stereo sum signal and stereo difference signal, whereas the FMX stereophonic broadcast signal further includes a compressed stereo difference signal and an FMX ID signal indicating the FMX stereophonic broadcast signal. The FM/FMX stereophonic receiver has a stereo demodulator for receiving said broadcast signal and for producing left and right stereo signals, a detector for detecting the field strength of the receiving signal, and a noise reducer, which may be a circuit for changing the mode from stereophonic mode to monaural mode or a high cut circuit for attenuating the signals of high frequency region, for reducing noise signals contained in the left and right stereo signals. The FM/FMX stereophonic receiver further has a detector for detecting the FMX ID signal and a disabling circuit for disabling the noise reducer when the FMX ID signal is detected by the detector. Instead of the disabling circuit, a timing control circuit may be provided for changing the timing at which the noise reducer starts to activate in response to the detection of the FMX ID signal.

FM/FMX stereophonic receiver

In an AM stereo receiving apparatus for decoding an AM stereo broadcasting signal of an ISB system, an envelope detecting circuit 6 detects an output of an intermediate frequency amplifying circuit 5 and a DC removing circuit 7 removes a DC component therefrom, so that a stereo sum signal (L+R) is obtained. A quadrature detecting circuit 9 detects quadrature of the output of the intermediate frequency amplifying circuit 5. A multiplying circuit 10 multiplies the stereo sum signal (L+R), which is amplified a times as much by a first amplifying circuit 8, and the output of the quadrature detecting circuit 9. An addition circuit 12 adds the output of the quadrature detecting circuit 9, which is amplified b times as much by a second amplifying circuit 11, and the output of the multiplying circuit 10. The output of the addition circuit 12 becomes a stereo difference signal (L-R) by appropriately setting the amplification factor a of the first amplifying circuit 8 and the amplification factor b of the second amplifying circuit 11.

Apparatus and method for decoding an AM stereo broadcasting signal of an

An AM stereo receiver applicable to receive AM signals containing ID signals which represent different AM stereo systems. The AM stereo receiver includes an IF circuit for generating an IF signal based on a received signal, a PLL circuit for locking the frequency of the IF signal, a clock circuit for generating a clock signal based on a signal obtained from the PLL circuit, and ID signal detector for detecting any one of the ID signals and for producing a detected ID signal. A circuit for distinguishing which one of the different AM stereo systems does the detected ID signal represent includes a pulse generator for generating a first pulse signal having a pulse width as a function of the frequency of the detected ID signal, a counter for counting the number of the clock pulses occurring during said first pulse signal, and distinguish circuit for distinguishing each detected ID signal from different ID signals based on the counted result of the counter.

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Gunma-ken, Japan

Masashi Arai