Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Masashi Agata

Hironori Akamatsu

Toshio Yamada

Masanori Shirahama

Hirohito Kikukawa

Naoki Kuroda

Toshiaki Kawasaki

Shunichi Iwanari

Ryuji Nishihara

Akihiro Sawada

Hisakazu Kotani

Kazunari Takahashi

Hiroyuki Yamauchi

Tsutomu Fujita

Ichiro Nakao

Makoto Kojima

Atsushi Fujiwara

Osamu Ichikawa

Hiroyuki Sadakata

Tomohiro Kurozumi

Kazuhiro Matsuyama

Toshihiro Inokuchi

A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in series so as to successively transfer data. A test circuit tests the redundant memory, and serially outputs relief information for relieving a defective cell. The relief processing section stores the relief information into the shift register circuits using a data transfer operation thereof.

Redundant memory incorporating serially-connected relief information storage

A fuse device and a program transistor are connected in series with each other. A flip-flop turns ON, in response to a start signal, the program transistor to start program of the fuse device. A 2-input NAND circuit outputs an end signal at a time point where change in a resistance value of the fuse device is increased to reach a predetermined level while monitoring change in the resistance value of the fuse device through change in a voltage at a junction point of the fuse device and the program transistor. The flip-flop turns OFF, in response to the end signal, the program transistor to automatically terminate the program of the fuse device. Thus, the resistance value of the fuse device is increased to the predetermined level in a minimum program time.

Semiconductor integrated circuit

Selection signals output from a decoder are selectively set at High according to the states (blown or not blown) or fuses in bit cells in a cell group specifying circuit. Then, one of transistor gates is turned ON so that a data bit cell group in/from which data is written and read out is selected. Accordingly, stored data can be rewritten multiple times by sequentially blowing the fuses in the cell group specifying circuit.

Semiconductor memory device

Provided is a semiconductor memory, comprising: a voltage converting circuit which voltage-converts a resistance difference between a first and a second resistance elements; a voltage comparing circuit which outputs an output corresponding to the voltage conversion; a latch circuit for holding the output of the voltage comparing circuit; and a switch circuit which cuts and connects the voltage converting circuit and the voltage comparing circuit.

Semiconductor memory

A semiconductor memory device includes: first and second bit cells for storing complementary data; a scan circuit for outputting a selected data signal; a bit-cell selector receiving the output of the scan circuit and selecting one of the bit cells; and a data write controlling circuit for controlling data writing. Write paths for all the bit cells for storing '0' are not selected and data is written only in a bit cell for storing '1', so that write operation performed in steps is achieved.

Nonvolatile semiconductor memory device and method for fabricating the same

A semiconductor integrated circuit device includes: first and second nonvolatile memory elements; a first amplifier for amplifying an output signal from the first nonvolatile memory element to output the amplified signal; and a second amplifier for outputting to the first amplifier a control signal generated by amplifying an output signal from the second nonvolatile memory element. The second amplifier fixes the output signal from the first amplifier at a high potential or a low potential based on data stored in the second nonvolatile memory element.

Semiconductor integrated circuit device and method for testing the same

In a normal operation, an output of a differential amplifier for amplifying a difference between first and second bit cells is output as readout data. In a test mode, when a first control signal is set to be 'H', the output of the differential amplifier is fixed to be 'H' and thus an output of the first bit cell is read out through gates.

A port A of the path including a first transistor of a memory cell to be accessed, a first bit line pair, a first column selection switch and a data line pair interleaves with a port B of the path including a second transistor of the memory cell to be accessed, a second bit line pair, a second column selection switch and the data line pair in two cycles of a clock. A read amplifier amplifies data transferred from a bit line pair to the data line pair and outputs the resultant data to an input/output buffer in one cycle of the clock. The input/output buffer outputs the data received from the read amplifier to the outside in one cycle of the clock.

A nonvolatile semiconductor memory device includes: a first bit cell including a first MOS transistor whose source and drain are connected to form a first control gate and a second MOS transistor which has a floating gate in common with the first MOS transistor; a second bit cell including a third MOS transistor whose source and drain are connected to form a second control gate and a fourth MOS transistor which has a floating gate in common with the third MOS transistor; and a differential amplifier which receives input signals from drains of the respective second and fourth MOS transistors.

Nonvolatile semiconductor memory device

The layout of the semiconductor storage circuit is generated by placing, along a word line direction, a desired number of a circuit extension units each of which includes a data access circuit section, memory cell sub arrays and a power circuit section arranged along a bit line direction. The data access circuit section is driven by a driver circuit provided in the data access circuit section, and the driving operation of the driver circuit is controlled by a driver circuit provided in a control circuit section. Also, a voltage supplying operation of the power circuit section is controlled by a driver circuit provided in a power control circuit section.

Semiconductor storage circuit and layout method for the same

Data reading speed of a DRAM is enhanced without causing an increase in the power consumption and in the chip area. To that end, when data is read, a pair of bit lines is precharged to a GND level, while a dummy cell is charged at a power supply voltage. Immediately after a word line and a dummy word line are activated and their respective potentials are increased by the threshold voltage of an access transistor, a main capacitor and a dummy capacitor are electrically connected to the bit lines, thereby allowing the data to fade in. The resultant potential difference between the pair of bit lines is detected and amplified by a sense amplifier, thereby enabling the data to be read. The capacitance of the dummy capacitor is about half of that of the main capacitor, so that the dummy capacitor can be precharged at the power supply voltage.

Semiconductor memory circuit

The semiconductor memory device includes: a memory cell including a capacitor having a charge storage node and a first MIS transistor and a second MIS transistor each having a source connected to the charge storage node; a first word line and a first bit line respectively connected to the gate and the drain of the first MIS transistor; a second word line and a second bit line respectively connected to the gate and the drain of the second MIS transistor; and a timer circuit for generating a periodic signal having a predetermined period. The first word line or the second word line is activated in response to the periodic signal.

A semiconductor memory device has a plurality of memory cells each having a first transistor, a second transistor having a source or drain connected to one portion of the source or drain of the first transistor, and a third transistor having a source or drain connected to the other portion of the source or drain of the first transistor. The first transistor accumulates, in the channel thereof, charges transferred from the second and third transistors.

A semiconductor memory device that enables data buses to operate at high speed by reducing wiring capacitance and interference noise between data bus lines is provided. A semiconductor memory device includes a read-only data bus which is formed in a first metal layer and has plural pairs of read lines precharged to an arbitrary voltage and two lines in a pair transmitting complementary read signals. A write-only data bus, which is positioned in parallel with the read-only data bus, is formed in a second metal layer different from the first metal layer and has plural pairs of write lines precharged to an arbitrary voltage, and two lines in a pair transmitting complementary write signals.

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Osaka, Japan

Masashi Agata