Matsushita Electric Industrial Co., Ltd.

Masaru Uya

Kinji Kawamoto

Takuya Sayama

Satoshi Takahashi

Norihiko Mizobata

Katsuyuki Kaneko

Takeshi Kawano

Takeshi Ichise

Yoshito Nishimichi

Taizou Tsujimoto

Masao Tsukamoto

Taizo Tsujimoto

An improved full subtracter is disclosed which receives a minuend signal A having a weight of +1, a subtrahend signal B having a weight of -1 and a borrow input signal Xi having a weight of -1 and provides a difference output: signal D having a weight of +1 and a borrow output signal Xo having a weight of -2. The full subtracter is composed of CMOS transistors such that both the signal D delay time and the signal Xo delay time are decreased by reducing the number of logic gate stages.

Full subtracter

Correspondingly to values stored in a plane memory in which the user can designate candidate pixels for a key color as desired, a data processor reads all items of pixel data indicative of the candidate pixels from a frame memory (memory for storing items of pixel data for one frame of an image) and calculates representative color data. A comparator compares the representative color data with the items of pixel data supplied in synchronism with a pixel clock signal to provide a chroma-key signal. The data processor receives new items of pixel data in a specified cycle, periodically recalculates and updates the representative color data, and supplies the updated representative color data to the comparator. As a result, an effective chroma-key signal is stably generated despite variations in background color.

Chroma-key signal generator

A 'city block' image subject to pointing is given as a first image V.sub.a. A 'hand' image serving as a pointer pointing something out on the first image V.sub.a is given as a second image V.sub.b. A mixer is provided which assigns a weight to pixel data of V.sub.a as well as to pixel data of V.sub.b, multiplies each pixel data by its weight, summing the results, and outputting the results as resulting pixel data. A comparator is provided which sends out a coincidence signal when a match is found between pixel data of V.sub.b and a 'hand' color requirement defined by given condition data. A data selector is provided which selects and outputs an output of the mixer when the comparator sends out a coincidence signal while otherwise it selects and outputs pixel data of V.sub.a, Pixels used to forming the 'hand' are specified from V.sub.b. With respect to such specified pixel, translucent synthesis of V.sub.a and V.sub.b is carried out. Pixels other than the specified pixels are used to display V.sub.a whereby a sharp synthetic image containing pointing information is obtained.

Image synthesizer and image pointing system

A dynamic-image displaying workstation provided with a display device for displaying an image, a video signal processing circuit for outputting dynamic-image data representing a dynamic image corresponding to a video signal, a first dual port memory for receiving and storing the dynamic-image data outputted from the video signal processing circuit, a second dual port memory for storing data representing pixels of an image to be displayed by the display device, and a third dual port memory for storing data representing a window area. The window area is an area of a window, to which the dynamic-image belongs, and is not covered by any other windows. The workstation is further provided with a fourth dual port memory for storing data representing a dynamic-image display effective area corresponding to the dynamic image represented by the dynamic-image stored in the first dual port memory, a data selector for receiving data read from the first dual port memory at a first input terminal thereof, and data read from the second dual port memory at a second input terminal thereof, for selecting one of the third and fourth dual port memories and receiving data read from the selected dual port memory at a third input terminal thereof, for selecting the data received at the first input terminal thereof if the data read from the third dual port memory is the data representing the window area, and the data read from the third dual port memory is the data representing the dynamic-image display effective area, for selecting the data received at the second input terminal thereof and for outputting a signal representing the selected data to the display device.

Workstation for displaying dynamic image with real-time special effects

An image blend circuit comprising a first image memory and a second image memory output pixel data according to pixel location information containing a pixel clock signal generated by an image location information supply unit, and a counter counts. Blend ratios are read from the counter and a blend ratio buffer. A data selector selects between these blend ratios according to a control signal from an attribute buffer and applies a selected blend ratio to a pixel blend unit. The pixel blend unit, depending upon the received blend ratio, translucently synthesizes or selects pixels from the first and second image memories. In an information processor, when opening a plurality of windows on a display screen produces an overlap field between the windows, such overlapped images are translucently blended for translucent image display. Therefore, the blend ratio can be set with less write information.

Weighted average circuit using digit shifting

Pixel data is selected from among first and second dynamic-image memories (DI1, DI2) and a static-memory (SI). In the invention, (a) first and second window area memories (WA1, WA2) for designating shapes and sizes of windows to which video dynamic-images are assigned respectively, (b) first and second dynamic-image area memories (DA1, DA2) for designating memory locations of data stored in both the dynamic-image memories, and (c) a priority control register for designating which video dynamic-image should be displayed in front when video dynamic-images overlap with each other are provided, whereby display for every pixel is executed according to a logical AND value of read-out data from WA1 and read-out data from DA1, a logical AND value of read-out data from WA2 and read-out data from DA2, and read-out data from the priority control register. Thus two video dynamicimages assigned to their respective windows are simultaneously displayed while subjecting them to overlap control, and special techniques including auto-zooming can be accomplished in real time.

Workstation for simultaneously displaying overlapped windows using a

A foreground live-video image, made up of a 'blue back' part, a 'hand/arm' part, and a 'shadow' part of the 'hand/arm' part, is chroma-key composited with a background live-video image. The 'blue back' part is displayed to be transparent on the display screen. The 'hand/arm' part is displayed to be opaque. The 'shadow' part is displayed to be translucent. Whereas a first comparator determines a key color of the 'blue back' part, a second comparator determines a key color of the 'shadow' part. According to the output code of the first and second comparators, a data selector selects, pixel data of the background live-video image (Va) for the 'blue back' part, pixel data of the foreground live-video image (Vb) for the 'hand/arm' part, and pixel data found by multiplying each of the pixel data of Va and the pixel data of Vb by a respective weight and summing those products, as respective output pixel data. The 'hand/arm' part may be displayed to be translucent by changing the output code relating to the 'hand/arm' part by a code converter.

Chroma-key live-video compositing circuit

A tone source system for a superior electronic musical instrument suitable for an LSI application in which the wave data can be provided in a time division multiplex form, or the envelope data can be provided in a time division multiplex form in a synchronous relationship with it, and the wave data to which the envelopes are attached can be provided in a time division multiplex form through multiplication of the data.

Electronic musical instrument

A FIFO memory using one of the ports of a RAM having two or more ports for writing and another port for reading is disclosed. Writing into the FIFO memory is done instantly, while reading from the FIFO memory is effected by holding the output of the preliminarily accessed RAM until the end of a reading operation. The output of the RAM is updated by a request from outside and according to the state of the FIFO memory, and this operation is done simultaneously with reading or writing.

First-in-first-out memory capable of simultaneous readings and writing

An integrated circuit having a latch circuit with a selection function includes a selection circuit having a plurality of logic circuits each capable of presenting three output states depending on a selection signal supplied thereto, a latch circuit having a bistable circuit composed of first and second logic inverting circuits, and a connection system for supplying an output of the selection circuit to an input of the latch circuit. An output resistance of the second logic inverting circuit is set to be at least ten times as high as an output resistance of any one of the logic circuits which make up the selection circuit.

Integrated circuit having latch circuit with multiplexer selection

A parallel binary adder has several blocked adders, wherein numbers of bits of adders are selected to be larger in higher order blocks than lower order blocks, thereby addition in all blocks will finish at the same time, thereby undue waiting time between the completion of the addition in several blocks can be eliminated, and thereby a faster parallel binary adder is obtainable.

Parallel binary adder

In a high speed latching circuit (C) for selectively receiving one or plural slowly changing input data signals and latching them at high speed, one or plural first CMOS FETs (31, 33, 35, 37) and one or plural second CMOS FETs (32, 34, 36, 38) of p-conductivity type are connected in series respectively to form one or plural series connections (31+32, 33+34, 35+36, 37+38), wherein selection signals are given to the gates of the first CMOS FETs, input data signals are given to the gates of the second CMOS FETs and a flip-flop (30+39+41) is driven by selected one of the series connections.

MOS register for selecting among various data inputs

A full adder is constituted with complementary MOS FETs, wherein delay time of adding time and carry signal delay time are shortened as a result of reduced number of stages of signal processing gates.

Full adder

A Schmitt trigger circuit uses an inverter and at least four transistors connected so as to ensure that its threshold voltages can optionally be set, its hysteresis voltage width can be sufficiently broad, and flow of steady-state current can be prevented.

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Osaka, Japan

Masaru Uya