Oki Electric Industry Co., Ltd.

Nippon Telegraph and Telephone Public Corporation

Masaru Uesugi

Shizuo Cho

Tsuneo Takano

Nobuaki Ieda

Yoshio Otsuki

A semiconductor memory circuit in which data are stored in dynamic type memory cells located at cross-points of bit and word lines, and are refreshed within a predetermined time by a sense amplifier so as to hold the thus stored data includes a first bit line connected to a first sense node of the sense amplifier. A second bit line is connected to a second sense node of the sense amplifier. A first switching circuit having a first terminal is disposed between the first bit line and the first sense node, for coupling the first bit line with the first sense node in response to a first control signal applied to the first terminal. A second switching circuit having a second terminal is disposed between the second bit line and the second sense node, for coupling the second bit line with the second sense node in response to a second control signal applied to the second terminal. A first control line is coupled to the first terminal and isolated from the second switching circuit and the second bit line, for providing the first control signal. A second control line is coupled to the second terminal and isolated from the first switching circuit and the first bit line, for providing the second control signal.

Semiconductor memory circuit

A semiconductor memory has a matrix of memory cells crossed by word lines and bit lines. In each group of eight adjacent bit lines, a first sense amplifier is coupled to the first and sixth bit lines, a second sense amplifier to the third and eighth bit lines, a third sense amplifier to the second and fifth bit lines, and a fourth sense amplifier to the fourth and seventh bit lines. The first and third sense amplifiers are located side by side on one side of the memory matrix, between the second and fifth bit lines. The second and fourth sense amplifiers are located side by side on the opposite side of the memory matrix, between the fourth and seventh bit lines.

Semiconductor memory with improved sense amplifier layout

A semiconductor memory device has pairs of complementary bit lines connected to pairs of complementary data bus lines via transfer elements controlled by column lines. The bit lines are arranged so that mutually adjacent pairs of bit lines are connected to the same pair of data bus lines at a pair of common nodes. The transfer elements for each such mutually adjacent pair of bit lines are controlled by different column lines.

Semiconductor memory device

A semiconductor memory circuit includes a plurality of bit line pairs each having intersecting portions where the paired bit lines intersect each other, and a plurality of pairs of memory word lines intersecting the bit lines in a direction substantially perpendicular to the bit lines. A plurality of memory cells are individually connected to the memory word lines and bit lines at intersections of one of the memory word lines of the individual memory word line pairs and one of the bit lines of the individual bit lines pairs and at intersections of the other of the paired memory word lines and the other of the paired bit lines for storing charges each being associated with data to be stored. A pair of dummy word lines are interposed between the intersecting portions of the bit lines and intersect the bit line pairs in a direction substantially perpendicular to the bit line pairs. A plurality of dumy cells are individually connected between the dummy word line pairs and the bit line pairs at intersections of one of the dummy word lines of the individual word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired dummy word lines and the other of the paired bit lines.

Semiconductor memory circuit having dummy cells connected to twisted bit

A reference voltage generating circuit in a CMOS semiconductor integrated circuit comprises a first reference voltage circuit for generating a first reference voltage by means of a MOS transistor having a first channel type, a second reference voltage circuit for generating a second reference voltage by means of a MOS transistor having a second channel type, and a comparator circuit for comparing the first and second reference voltages and feeding back the output corresponding to the result of the comparison, to the first reference voltage circuit to produce a third reference voltage.

Reference voltage generating circuit

A semiconductor memory such as a dynamic RAM (Random Access Memory) implemented by complementary MOS (CMOS) transistors includes a plurality of bit line pairs each constituted by a first and a second complementary bit line for transferring data, and a plurality of word lines extending across the bit line pairs. A plurality of memory cells are located at the intersecting points of the bit line pairs and word lines and connected to the latter for storing data therein. A plurality of sense amplifier circuits are each associated with respect to one of the bit line pairs for sensing potentials on a first and a second node associated with the bit line pair and amplifying the sensed potentials. Each of the sense amplifier circuits includes a first and a second sense amplifier of opposite polarity. A plurality of first field effect transistors (FETs) each has a source-drain path for connecting to the first node the first bit line of respective one of the bit line pairs. A plurality of second FETs each has a source-drain path for connecting to the second node the second bit line of respective one of the bit line pairs. The plurality of first and second field effect transistors individually have commonly connected control electrodes to which a gate signal is applied. The plurality of first and second field effect transistors are complementarily controlled in response to the gate signal to transfer one of the potentials on the first and second bit lines to one of the first and second sense amplifiers.

CMOS RAM having a complementary channel sense amplifier

A semiconductor memory circuit includes a plurality of bit line pairs each having intersecting portions where the paired bit lines intersect each other, and a plurality of pairs of memory word lines intersecting the bit lines in a direction substantially perpendicular to the bit lines. A plurality of memory cells are individually connected to the memory word lines and bit lines at intersections of one of the memory word lines of the individual memory word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired memory word lines and the other of the paired bit lines for storing charges each being associated with data to be sorted. A pair of dummy word lines are interposed between the intersecting portions of the bit lines and intersect the bit line pairs in a direction substantially perpendicular to the bit line pairs. A plurality of dummy cells are individually connected between the dummy word line pairs and the bit line pairs at intersections of one of the dummy word lines of the individual word line pairs and one of the bit lines of the individual bit line pairs and at intersections of the other of the paired dummy word lines and the other of the paired bit lines.

A semiconductor random access memory device having input terminals for receiving multi-bit data and output terminals for transmitting multi-bit data includes a memory cell matrix connected to a number of pairs of data lines and including a number of memory cells. Also included is an address decoder circuit which is responsive to an external address signal for providing address selection signals and a number of data input control circuits for receiving both 1-bit data signal and 1-bit signals of the multi-bit data and for providing as a pair of complementary signals either the 1-bit data signal or the one bit signal of the multi-bit data signal in response to various signals input thereto. A number of data input/output switching circuits and bit data output control circuits and 1-bit data output circuits and bit signal output control circuits are also provided for properly outputting either the 1-bit data or one bit signal of the multi-bit data from the output of the semiconductor random access memory device.

Semiconductor random access memory device having switchable input and

The buffer circuit is provided with a high sensitivity balanced type flip-flop circuit and a capacative coupling provided by MOS capacitance, and a load drive circuit utilizes bootstrap effect, thus producing complementary signals having a MOS level from a TTL address input signal.

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Tokyo, Japan

Masaru Uesugi