Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Masaru Sugimoto

Teruhiko Funakura

Yasuhide Nakase

Hisaya Mori

Toshiaki Tarui

Hidekazu Nagasawa

Tomohiro Nishimura

In a test circuit, a determination circuit conducts a function test to determine whether timing of a slope section of waveform of an analog signal ANS of a measurement target device is within a range of specifications. An ADC performs AD-conversion only when a potential of analog signal ANS is within a range between reference potentials VOL, VOH. An analysis unit analyzes digital data from the ADC, and conducts a sloping waveform test to evaluate a sloping state of the waveform of analog signal ANS. Therefore, the slope section of the waveform of analog signal ANS of the device can be subjected to AD-conversion in a voltage range divided in arbitrary number of sections within a range of arbitrary voltage amplitude without requiring a large-capacity storage circuit. The function test by a determination circuit and the sloping waveform test by the analysis unit can be performed in parallel.

Test circuit for evaluating characteristic of analog signal of device

The interface circuit includes n buffer circuits, switches for connecting an external pin of a tester to input nodes of n buffer circuits and connecting output nodes of n buffers respectively to n DUTs when a signal is provided from the tester to n DUTs, and successively connecting n DUTs to the external pin of the tester by a prescribed time period when voltage-ampere characteristics of n DUTs are measured. Therefore the number of devices that can be measured by the tester at a time can be increased by n times. As a result, the test cost can be reduced and the test accuracy can be improved.

Interface circuit coupling semiconductor test apparatus with tested semiconductor device

An LSI testing apparatus of the invention comprises: a plurality of pins P , P , . . . PN; function units and which supply the pins with LSI testing signals, which have functions for making judgments on tests, and which are furnished for each of the pins; and clock mask function units A and B furnished on the input side of each function unit. Upon testing, any unused pin and function are detected so as to mask the clock mask function unit corresponding to the detected pin and function, whereby power dissipation is reduced in terms of unused pins and functions.

LSI testing apparatus

A waveform and timing generation circuit,, a skew circuit,, and a pin driver,are provided for each of a plurality of I/O terminals,corresponding respectively to a plurality of pins furnished on an LSI. A relay,and a loop control circuit,are provided to feed an output signal of the pin driver,back to an input side of the waveform and timing generation circuit,. A skew board,is used to adjust the skew circuit,, whereby the initial timing calibration is carried out. With the skew circuit,thus adjusted, oscillations are generated over the feedback path, and the number of resulting pulses is counted (to obtain pulse cycles). When the skew circuit,is adjusted so that the pulse count above matches the number of pulses generated during oscillations, a simplified form of timing calibration is implemented.

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Hyogo, Japan

Masaru Sugimoto