Toyota Jidosha Kabushiki Kaisha

Denso Corporation

Kabushiki Kaisha Toyota Chuo Kenkyusho

Masaru Senoo

Yasuhiro Hirabayashi

Yusuke Yamashita

Akitaka Soeno

Satoru Machida

Jun Okawara

Hiroshi Hosokawa

Jun Saito

Masanori Miyata

Yoshifumi Yasuda

Tsuyoshi Nishiwaki

Yuma Kagata

Takashi Kuno

Yuki Yakushigawa

Kyosuke Miyagi

Koichi Nishikawa

Noriyuki Kakimoto

Shuhei Oki

Tomoo Yamabuki

Tomohiko Sato

Shuji Yoneda

Toshitaka Kanemaru

Kenta Hashimoto

Satoshi Kuwano

Takaya Nagai

Tomoki Akai

Yuuma Kagata

In a semiconductor device, a semiconductor substrate has an IGBT region and a FWD, and includes a first conductivity type drift layer, a second conductivity type base layer disposed on the drift layer, a second conductivity type collector layer disposed opposite to the base layer with respect to the drift layer in the IGBT region, and a first conductivity type cathode layer disposed opposite to the base layer with respect to the drift layer in the FWD region. The collector layer includes an extension portion that covers only a part of the cathode layer on a side adjacent to the drift layer. Alternatively, the collector layer includes an extension portion that entirely covers a region of the cathode layer adjacent to the drift layer, and has an area density of 3.5×10cmor less.

Semiconductor device

A semiconductor device includes an IGBT region in which an IGBT element is formed and an FWD region in which an FWD element is formed. The IGBT region includes a first region and a second region different from the first region. The FWD region and the first region of the IGBT region have a carrier extraction portion that facilitates extraction of carriers injected from a second electrode compared to the second region when a forward bias for causing the FWD element to operate as a diode is applied between a first electrode and the second electrode.

A semiconductor device having IGBT, FWD and separate cell regions in a common semiconductor substrate, includes: a drift layer; a base layer; trench gate structures; an emitter region; a collector layer; a cathode layer; a first electrode; and a second electrode. The IGBT region having a first gate electrode in first and second IGBT trenches with a grid pattern is on the collector layer, and the FWD region with a second gate electrode in first and second FWD trenches with a grid pattern is on the cathode layer.

A semiconductor apparatus includes a semiconductor substrate provided with a plurality of diode ranges and a plurality of IGBT ranges. The IGBT ranges and the diode ranges are alternately arranged along a first direction in plan view of the semiconductor substrate along a thickness direction of the semiconductor substrate. Each diode range is provided with a plurality of n-type cathode regions and a plurality of p-type current-limiting regions in a range of being in contact with a lower electrode. The cathode regions and the current-limiting regions are alternately arranged along a second direction intersecting the first direction in each diode range. Each IGBT range is provided with a p-type collector region in a range of being in contact with the lower electrode. The collector region in each IGBT range is in contact with each cathode region in the adjacent diode range.

Semiconductor apparatus

A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode provided above the semiconductor substrate; a sense anode electrode provided above the semiconductor substrate; a resistance layer provided above the semiconductor substrate and having a resistivity higher than the sense anode electrode; a lower main electrode provided below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode comprises a first anode region of a p-type connected to the sense anode electrode via the resistance layer and a first cathode region of an n-type connected to the lower main electrode.

Semiconductor device including a switching element and a sense diode

A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode electrode located above the semiconductor substrate; a first resistance layer located above the semiconductor substrate, having resistivity higher than resistivities of the upper main electrode and the sense anode electrode, and connecting the upper main electrode and the sense anode electrode; and a lower main electrode located below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode includes a p-type first anode region connected to the sense anode electrode and an n-type first cathode region connected to the lower main electrode.

A switching device including a semiconductor substrate including a trench (gate electrode) extending in a mesh shape is provided, and the upper surface of the semiconductor substrate is covered by the interlayer insulating film. Within an element range a contact hole is provided in an interlayer insulating film above each cell region while within a surrounding range an entire upper surface of each cell region is covered by the interlayer insulating film. The first metal layer covers the interlayer insulating film, and has recesses above the contact holes. The insulating protective film covers an outer peripheral side portion of the first metal layer within the surrounding range. The second metal layer covers the first metal layer within an opening of the insulating protective film. Within the surrounding range, a second conductivity-type region extending to below lower ends of the trench and is electrically connected to the body region, is provided.

Switching device

A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a semiconductor substrate having a gate trench and a dummy trench. The semiconductor substrate includes emitter, body, barrier and pillar regions between the gate trench and the dummy trench. The emitter region is an n-type region being in contact with the gate insulating film and exposed on a front surface. The body region is a p-type region being in contact with the gate insulating film at a rear surface side of the emitter region. The barrier region is an n-type region being in contact with the gate insulating film at a rear surface side of the body region and in contact with the dummy insulating film. The pillar region is an n-type region connected to the front surface electrode and the barrier region.

A semiconductor device includes a diode and a semiconductor substrate. The diode includes a p-type anode region and an n-type cathode region. A lifetime control layer is provided in an area within the cathode region. The area is located on a back side than a middle portion of the semiconductor substrate in a thickness direction of the semiconductor substrate. The lifetime control layer has crystal defects which are distributed along a planar direction of the semiconductor substrate. A peak value of a crystal defect density in the lifetime control layer is higher than a crystal defect density of a front side region adjacent to the lifetime control layer on a front side of the lifetime control layer and a crystal defect density of a back side region adjacent to the lifetime control layer on a back side of the lifetime control layer.

Semiconductor device with improved reverse recovery characteristics

An IGBT includes a rectangular trench including first to fourth trenches and a gate electrode arranged inside of the rectangular trench. An n-type emitter region includes a first emitter region being in contact with the first trench, and a second emitter region being in contact with the third trench. A body contact region includes a first body contact region being in contact with the second trench, and a second body contact region being in contact with the fourth trench. A surface body region is in contact with the trenches in ranges from connection portions to the emitter regions.

IGBT

In a plan view of a semiconductor substrate, the semiconductor substrate includes a pillar exposing area in which the pillar region is exposed on the front surface of the semiconductor substrate, a pillar contacting area in which the pillar region is in contact with a deeper side of the anode contact region, and an anode contacting area in which the anode region is in contact with the deeper side of the anode contact region. In a direction along which the pillar contacting area and the anode contacting area are aligned, a width of the pillar contacting area is smaller than a width of the anode contacting area.

An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region.

IGBT and method of manufacturing the same

A semiconductor device includes a semiconductor layer and a trench gate portion that extends toward a deep portion from a front surface of the semiconductor layer. The semiconductor layer includes an island region surrounded by the trench gate portion. A first side surface of the trench gate portion and a second side surface of the trench gate portion are in contact with the island region. A first conductivity type contact region that includes a first contact region that is in contact with the first side surface and a second contact region that is in contact with the second side surface is provided in the island region. Moreover, a second conductivity type contact region that is in contact with the trench gate portion at a position between the first contact region and the second contact region is provided in the island region.

A reverse conducting IGBT is provided with a trench gate member that is provided in an IGBT region and has a lattice-pattern layout, and a trench member that is provided in a diode region and has a stripe-pattern layout. The diode region of the semiconductor substrate includes an anode region of a first conductive type, a drift region of a second conductive type and a barrier region of the second conductive type. The barrier region is electrically connected to a top surface electrode via a pillar member that extends from a top surface of the semiconductor substrate.

Reverse conducting IGBT

A semiconductor layer of a reverse conducting insulated gate bipolar transistor is provided with a drift region of a first conductive type, a body region of a second conductive type that is disposed above the drift region, and a barrier region of the first conductive type that is disposed in the body region and electrically connects to the emitter electrode via a pillar member which extends from the one of main surfaces of the semiconductor layer. The barrier region is not contact with a side surface of the insulated trench gate.

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Okazaki, Japan

Masaru Senoo