Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Fujitsu Vlsi Limited

Masaru Sawada

Takao Sugawara

Toshihiko Morita

Toshio Ito

Motomu Takatsu

Tsunehiko Moriuchi

Manabu Nakano

Hiroko Murakami

Yoshitaka Nakata

Ian Juso Dedic

Sanroku Tsukamoto

Norio Murakami

Koji Horibe

Hideaki Tanishima

Hiroko Haraguchi

Kenichi Yamakura

Tsuyoshi Tomita

Hideaki Kondo

Fumiaki Uematsu

Toshiaki Endo

Kuniyoshi Kamei

Kenji Yamada

Akihiro Yamazaki

Shigetaka Asano

Kiichiro Iga

Kazuyoshi Kikuta

Syoichi Masui

A PLL includes: a charge-pump equalizer which has a plurality of charge pumps generating charge currents according to phase-difference signals, each being generated by delaying the phase-difference signal by different times, adds and outputs the charge currents generated by the charge pumps; a replica circuit, having ideal characteristics of a loop filter and a voltage controlled oscillator, which input a digital value having phase difference of the phase-difference signals, and generates a replica output according to the ideal characteristics; and a coefficient generating circuit which smoothes correlation values of the difference signals and the phase-difference signals to generate charge pump coefficients, and negatively feeds back the same to the plurality of charge pumps. The charge pumps generate the charge currents each having current values corresponding to the charge pump coefficients.

A transmitting and receiving circuit includes a transmitting side amplifier circuit amplifying a transmission signal transmitted from an antenna, a receiving side amplifier circuit amplifying a reception signal received by the antenna and being electrically connected to the a transmitting side amplifier circuit, a first matching circuit matching the antenna and the transmitting side amplifier circuit, a second matching circuit matching the antenna and the receiving side amplifier circuit, a first current source circuit capable of controlling an operating state and setting a first connection point between the first matching circuit and an output terminal of the transmitting side amplifier circuit to a given voltage, and a second current source circuit capable of controlling an operating state and setting a second connection point between the second matching circuit and an input terminal of the receiving side amplifier circuit to a given voltage.

Transmitting and receiving circuit

A filter circuit includes a low-pass filter and a calibration circuit calibrating a frequency characteristic of the low-pass filter. The calibration circuit includes a negative feedback circuit and a control circuit.

filter circuit and semiconductor device

A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.

Information recording and reproducing apparatus and method, and signal decoding circuit for performing timing recovery

When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input registerand a second input register, bits before and after the zero run is transferred to a temporary registervia a bus for zero run removalto be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.

Encoder and decoder using run-length-limited code

In a training operation for optimizing a multiplication coefficient for each tap of an FIR equalizer equalizing a read signal read from a recording medium, as a restricted coefficient updating vector applied for updating the multiplication coefficient for each tap of an FIR filter, a vector is utilized which is obtained by projecting, onto a plane perpendicular to a predetermined restricting conditioning vector, a coefficient updating vector determined based on an equalizer error between the output of the FIR equalizer and a reproduction output determined therefrom and a delayed input value for each tap of the FIR equalizer. As the restricting conditioning vector, a vector is utilized which is a difference between a subsequent coefficient vector obtained in the same condition immediately subsequent to and an antecedent coefficient vector obtained in the same condition immediately antecedent to a reference coefficient comprising the multiplication coefficient for the equalizer obtained upon calculating the equalizer error.

Training method for recording medium reproduction equalizer and recording medium reproduction apparatus

An encoded-bit-string generating unit generates a bit string encoded by scrambling an input bit string. A direct-current-component evaluating unit selects a bit string having a predetermined width in the bit string generated by the encoded-bit-string generating unit, while shifting bits one by one, and evaluates the direct-current component in the selected bit string. A bit-string extracting unit extracts a bit string with suppressed direct-current component, based on a result of an evaluation by the direct-current-component evaluating unit.

Encoder and decoder

A recording and reproducing apparatus includes an RLL encoder that encodes an information bit string to a code bit string and a RLL decoder that decodes the code bit string to the information bit string. The RLL encoder encodes the information bit string to the code bit string of a run-length-limited code at a high encoding rate satisfying a plurality of conditions of constraint regarding a string of successive zeros. The RLL decoder decodes the code bit string encoded by the RLL encoder to the information bit string.

Recording and reproducing apparatus

An information recording/reading apparatus employs a preamble to reproduce a clock used when recording information in a recording medium and reads the information out of the recording medium at a timing synchronized with a read signal. The preamble is split and recorded by replacing a middle portion of the preamble with data and a sync byte. While a first buffer is employed to delay signal data read out of the recording medium, a frequency offset detector detects a frequency offset using the split preamble.

Method of and apparatus for recording/reading information, circuit for recording/reading signal

A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.

Signal processor having feedback loop control for decision feedback equalizer

A semiconductor circuit includes a decision feedback equalizer (DFE) for waveform-equalizing an input signal and generating a waveform-equalized input signal. The DFE compares the waveform-equalized signal with a predetermined reference voltage to generate a decision signal having first and second decision values and an error signal which lies between the waveform-equalized signal and the decision signal. A dispersion value calculator is connected to the DFE, calculates first and second dispersion values of the first and second decision values of the decision signal using the error signal, and produces a compensation signal using the first and second dispersion values. An asymmetry compensator is connected to the DFE and the dispersion value calculator. The asymmetry compensator receives the input signal and corrects an asymmetry in the input signal in accordance with the compensation signal and supplies the corrected input signal to the DFE. The semiconductor device may be used in a hard disk control circuit.

Semiconductor device with decision feedback equalizer

A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of arithmetic operation blocks receive a plurality of digital input signals and perform different arithmetic operations on the received digital input signals, in parallel, to output operation result signals. The a control signal generator receives a plurality of digital input signals and generates a control signal based on the digital input signals. The selector selects one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.

Semiconductor integrated circuit device

A servo signal processing apparatus for processing a servo signal corresponding to servo information from a servo area on a recording medium for controlling a head. The servo area includes a servo mark area for storing a servo mark indicative of a head of the servo area, a gray mark area for storing a gray mark indicative of a head of information for position control for the head, and a gray code area for storing information. An A-D converter converts the servo signal to digital data. A digital filter filters the converted data based on a sampling clock, and outputs the filtered digital data. A servo mark detector detects a servo mark based on a continuity of a first predetermined logical value. A gray code decoder detects a gray code based on a continuity of a predetermined logical value. The gray code decoder decodes information stored in a gray code area following the detected gray mark.

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Kawasaki, Japan

Masaru Sawada