Victor Company of Japan, Limited

Masaru Moriyama

Nobuaki Takahashi

Kohei Sasamura

Kohhei Sasamura

A magnetic field generating apparatus for generating a biasing magnetic field applied to master and slave tapes superposed each other for transferring information signals recorded on the master tape to the slave tape, the apparatus comprises a rotary cylinder having a high magnetic permeability on its surface, a main magnetic pole disposed to confront the rotary cylinder for projecting the biasing magnetic field toward the rotary cylinder through a gap defined by a first predetermined distance, a sub-magnetic pole magnetically connected to the main magnetic pole, the master and the slave tapes are depressed to the rotary cylinder by compressed air, and an exciting source for exciting the main magnetic pole to generate the biasing magnetic field, wherein the sub-magnetic pole comprises at least one side-core disposed at a side of the main magnetic pole a second predetermined distance apart therefrom, the side-core confronts with and extends along the rotary cylinder, the second predetermined distance is substantially larger than the first predetermined distance, and a confronting area of the side-core facing to the rotary cylinder is substantially larger than a confronting area of the main magnetic pole facing to the rotary cylinder. An angle of the line of uniform flux density zone formed in front of the main magnetic pole with respect to a rotation axis of the rotary cylinder, can electrically be controlled by making the main magnetic pole being bifurcated to have two legs and exciting them differently each other.

Magnetic field generating apparatus for generating bias magnetic field

A digital signal reproducing apparatus comprises reproducing elements for reproducing digital signals from tracks of a magnetic tape having a guard band separating each of two adjacent tracks, which reproducing elements are arranged equidistant from each other along the tape width direction over a range which includes all of the tracks and guard bands, a parallel-to-serial converter supplied in parallel with outputs of the reproducing elements for performing a serial-to-parallel conversion and for producing a serial reproduced signal, a controller supplied with the serial reproduced signal for detecting a reproduced signal of a first track and for producing a pulse corresponding to the first track during a time period in which the outputs of those reproducing elements corresponding to a substantially uniform part of a magnetic field intensity distribution of the first track are obtained, which controller time-sequentially produces pulses corresponding to each of the tracks with a period corresponding to the track pitch, and an output circuit responsive to the output pulses of the controller for obtaining reproduced signals of the tracks and independently producing the reproduced signals of the tracks.

Digital signal reproducing apparatus

A digital signal reproducing apparatus comprises a reproducing head for reproducing from a magnetic tape digital signals which are magnetically recorded on n tracks of the magnetic tape, where n is a natural number greater than one, the magnetic tape has a guard band separating each of two adjacent tracks among the n tracks, the reproducing head comprises n reproducing element groups provided in correspondence with the n tracks and each of the n reproducing element groups comprises a plurality of reproducing elements arranged in the tape width direction over a range of a corresponding track and guard bands on both sides thereof, a selecting circuit for selectively obtaining outputs of those reproducing elements opposing a uniform part of the magnetic field intensity distribution of the corresponding track among outputs of the plurality of reproducing elements in each of the n reproducing element groups, which selecting circuit is provided for each of the n reproducing element groups, and an adder for adding outputs of the selecting circuit and for producing a reproduced signal from each of the n tracks.

A digital signal reproducing apparatus comprises a reproducing circuit for reproducing a recorded unipolar signal from a recording medium, an equalizer for subjecting the reproduced signal to a waveform equalization, a circuit for extracting a timing component having a period which is equal to one bit transmission period of the recorded unipolar signal from an output signal of the equalizer, a circuit for generating one or a plurality of clock signals which are in phase synchronism with the timing component and for forming one or a plurality of control signals by frequency-dividing the timing component by 1/2, a circuit for sampling and holding a peak value of the output signal of the equalizer for every one bit transmission period, a variable resistor for voltage-dividing the sampled and held signal to obtain a reference signal, a delay circuit for delaying the output signal of the equalizer, a comparing circuit for comparing the levels of the output signal of the delay circuit and the reference signal, and a circuit for producing a reproduced unipolar digital signal by controlling the pulse width and the pulse position of the output pulse signal of the comparing circuit by the one or a plurality of clock signals.

A self-bias circuit is employed for automatically changing the reference voltage of a comparator of an A/D converter of successive approximation type. The self-bias circuit is responsive to a voltage at a summing point where an input analog signal, an offset bias and an output analog signal from a D/A converter are added to each other. The self-bias circuit comprises a resistor and a capacitor so that the capacitor is charged by an average current passing through the resistor connected to the summing point, and the voltage across the capacitor will be used as the reference voltage of the comparator. When the input analog signal amplitude is small, the reference voltage is shifted so that noises superposed on the voltage at the summing point does not cause the comparator to produce an erroneous output signal with which the state of the MSB is undesirably changed. As the amplitude increases, the reference voltage rises for ensuring sufficient dynamic range and symmetrical operation for both positive and negative waves.

A/D Converter having a self-bias circuit

A magnetic reproducing system reproduces a recording two-valued code signal from a magnetic recording medium, and detects the signal level of the reproduced signal to reproduce a digital signal of a desired two-valued code, where the recording two-valued code signal is obtained by passing the digital signal of the above desired two-valued code through a converter and a delay circuit and then feeding back this digital signal to carry out a modulo-2 addition. The magnetic recording medium is recorded with the above recording two-valued code signal. The magnetic reproducing system comprises a magnetic head for reproducing the two-valued code recorded on the magnetic recording medium, an equalizer for performing wave-equalization of the signal reproduced by the magnetic head, and a signal detection circuit for detecting the signal level of a three-valued code signal obtained from the above equalizer, to produce a two-valued detection signal in which signal levels corresponding to '+1' and '-1' of the three-valued code signal is set to a signal level '+1' and a signal level corresponding to '0' of the three-valued code signal is set to a signal level '0', as a reproduced output signal of the digital signal.

Magnetic reproducing system for a digital signal

A D/A converting circuit comprises two data selectors and two D/A converters having an external reference input terminal. A decoder responsive to several bits including the MSB of the input digital signal to be converted into an analog signal is provided to detect whether the input digital signal represents an analog signal magnitude which is greater than the full-scale value of the analog signal or not, and thus expansion-nonexpansion operation of the D/A converting circuit is controlled so that an m-bit D/A converter can be used, as the first D/A converter, to handle an n-bit digital signal where n&gt;m. The first D/A converter receives m-bit information including the MSB in expansion mode, and receives m-bit information including the LSB in nonexpansion mode. The second D/A converter receives K-bit information (K=n-m) including the LSB of the input digital signal in expansion mode, and receives a predetermined digital data from a fixed data circut in nonexpansion mode. The second D/A converter performs D/A conversion by using a fixed voltage, and the output analog voltage of the second D/A converter is added to the fixed voltage prior to being fed to the first D/A converter as its reference voltage when expansion is required.

D/A Converting circuit having two D/A converters for decoding and

A matrix amplifying circuit comprises a first operational amplifier having an inverting and a non-inverting input terminal. The sum of the first and second channel signals is applied to the inverting terminal. The difference of the two channel signals is applied to the non-inverting terminal. The matrix amplifier substracts these sum and difference signals and a second operational amplifier adds them. This second amplifier has an inverting input terminal to which the sum signal and the difference signal are respectively supplied. These first and second operational amplifiers respectively produce first and second channel signals, as outputs thereof.

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Yamato, Japan

Masaru Moriyama