Hitachi, Ltd.

Masaru Koyanagi

Hideya Akashi

Yuji Tsushima

Yoshiki Murakami

Tadayuki Sakakibara

Disuke Yamane

A cache system comprising a cache tag bufferfor storing a part of a cache tag memory. When a memory processing request is issued from a processor, a cache control meansretrieves both of the cache tag memoryand the cache tag buffer. If a target cache block is present in the cache tag buffer, then, without waiting for a retrieval result of the cache tag memory, the cache control circuitaccesses the cache data memoryusing information of the cache block.

Cache system with a cache tag memory and a cache tag buffer

A cache controller stores pre-set variables for pre-fetch block size and stride value. A cache controller receives an access request for the main memory from the processor, and generates a pre-fetch request based an the access request and the variables. The cache controller reads data from main memory based on the generated pre-fetch request and writes this data to the cache memory.

Growing community of inventors

Hadano, Japan

Masaru Koyanagi