Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Toshiba Memeory Corporation

Kloxia Corporation

Masaru Koyanagi

Mikihiko Ito

Yasuhiro Hirashima

Ryo Fukuda

Kensuke Yamamoto

Katsuki Matsudera

Kenro Kubota

Junya Matsuno

Masato Dome

Kei Shiraishi

Kazuhide Yoneya

Yasuhiro Suematsu

Koji Hosono

Mitsuhiro Noguchi

Hiroyuki Kutsukake

Masahiro Yoshihara

Dai Nakamura

Takahiko Hara

Kenji Gomikawa

Takeshi Shimane

Fumiya Watanabe

Takashi Aoi

Akio Sugahara

Kazushige Kawasaki

Kazuyoshi Muraoka

Hiroaki Tanaka

Yutaka Takayama

Toshiki Hisada

Satoshi Tsukiyama

Yoshikazu Takeyama

Yoshiaki Takeuchi

Kaoru Nakagawa

Eiichi Makino

Satoru Takase

Natsuki Kushiyama

Shinya Okuno

Shigeki Nagasaka

Minoru Yamada

Maya Inagaki

Kazuhiko Satou

Tohru Kimura

Masafumi Nakatani

Souichi Sugiura

Kenichi Matoba

Manami Kudou

Satoshi Inoue

Akira Umezawa

Yuui Shimizu

Fumiyoshi Matsuoka

Ryosuke Matsuo

Mikihiko Itoh

Yasufumi Kajiyama

Tsuyoshi Etoh

Katsuya Okumura

Takeshi Nagai

Hiroaki Nakano

Yuji Nagai

Hiroaki Yamamoto

Masami Masuda

Noriyasu Kumazaki

Toshiyuki Kouchi

Katsumi Abe

Tsunetoshi Arikado

Hiromitsu Komai

Yutaka Shimizu

Yohei Yasuda

Shouichi Ozaki

Eiji Kozuka

Takehisa Kurosawa

Takashi Taira

Shintaro Hayashi

Yumi Takada

Zhao Lu

Shigefumi Ishiguro

Masafumi Uemura

Tadashi Onizawa

Itaru Yamaguchi

Taichi Wakui

Yashiro Suematsu

Minoru Yamda

Kazuhiro Hataoka

Koji Kuroki

Shoki Ito

Kentaro Watanabe

A semiconductor device includes a protection circuit electrically connected to a first interconnection and a second interconnection, a first voltage and a second voltage supplied to the first interconnection and the second interconnection, respectively. The protection circuit includes: a first resistor connected between the first interconnection and a first node; a first capacitor connected between the second interconnection and the first node; a second resistor connected between the second interconnection and a second node located; a second capacitor connected between the second interconnection and the second node, and connected in parallel to the second resistor; a third resistor connected between the first interconnection and a third node; and a third capacitor connected between the second interconnection and the third node.

Semiconductor device

A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

Semiconductor device having stacked chips

A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

Non-volatile semiconductor storage device

According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.

Semiconductor memory device

A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.

Memory device

A semiconductor device includes a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage. A second circuit is coupled to the first node and is configured to latch data based on a voltage of the first node; and a third circuit is coupled to the first node and is configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.

A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

A memory device includes a nonvolatile semiconductor memory cell array, a plurality of terminals through which control signals are received to control the memory device, an on-die termination circuit connected to at least one of the terminals and having a variable resistor, and a control circuit. The control circuit is configured to enable the on-die termination circuit in response to an enabling signal to enable the on-die termination circuit, with a resistance of the variableregistorresistorat different values depending on whether a control signal is asserted or deasserted when the enabling signal is received.

Nonvolatile semiconductor memory device and memory system having termination circuit with variable resistor

A semiconductor memory device includes a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal. The signal propagation circuit includes a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit, and further including a terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.

A semiconductor memory device includes a first and second substrates; and a first and second element layers respectively provided on an upper surface of the first and the second substrates. The first and second substrates respectively include a first and second vias. The first and second element layers respectively includes a first and second pads respectively electrically coupled to the first and second vias, and respectively provided on an upper surface of the first and second element layers. The upper surface of the second element layer is arranged so as to be opposed to the upper surface of the first element layer. The first and second pads are electrically coupled and symmetrically arranged with respect to a surface where the first and second element layers are opposed to each other.

A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.

Stacked chips comprising interconnects

A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.

Semiconductor storage device

According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.

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Tokyo, Japan

Masaru Koyanagi