Renesas Electronics Corporation

Renesas Technology Corp.

Tokyo Electron Limited

Hitachi, Ltd.

Oki Electric Industry Co., Ltd.

Masaru Kadoshima

Toshihide Nabatame

Masao Inoue

Hiroshi Umeda

Hiroyuki Takaba

Yoshiyuki Kawashima

Takaaki Suzuki

Katsuyuki Horita

Tomoichi Kamo

Jiro Yugami

Takaaki Kawahara

Koji Akiyama

Mitsuo Hayashibara

Kozo Sakamoto

Masahiko Fujisawa

Tatsunori Kaneoka

Kazushige Kohno

Toshiya Doi

Shigeoki Nishimura

Tetsuo Fujiwara

Masaharu Mizutani

Shinsuke Sakashita

Morifumi Ohno

Seiji Watahiki

Ichiro Yamakawa

Yasuhiko Murata

Seizi Koike

A memory cell, which is a nonvolatile memory cell, includes a gate dielectric film having charge storage layer capable of holding charges, and a memory gate electrode formed on the gate dielectric film. The charge storage layer includes an insulating film containing hafnium, silicon, and oxygen, an insertion layer formed on the insulating film and containing aluminum, and an insulating film formed on the insertion layer and containing hafnium, silicon, and oxygen.

Semiconductor device including memory using hafnium and a method of manufacturing the same

To improve the performance of a semiconductor device, the semiconductor device includes an insulating film portion over a semiconductor substrate. The insulating film portion includes an insulating film containing silicon and oxygen, a first charge storage film containing silicon and nitrogen, an insulating film containing silicon and oxygen, a second charge storage film containing silicon and nitrogen, and an insulating film containing silicon and oxygen. The first charge storage film is included by two charge storage films.

Semiconductor device and manufacturing device of the same

In a semiconductor device, a width of a second epitaxial layer is greater than a width of a first epitaxial layer, and a thickness of an end portion of the second epitaxial layer, which is in contact with an element isolation portion, is smaller than a thickness of an end portion of the first epitaxial layer, which is in contact with the element isolation portion, and a second shortest distance between the element isolation portion and a second plug is greater than a first shortest distance between the element isolation portion and a first plug.

Semiconductor device and method of manufacturing thereof

The present invention makes it possible, in a manufacturing process of a semiconductor device, to inhibit: impurities from diffusing from a substrate to a semiconductor layer; and the withstand voltage of a transistor from deteriorating. In the present invention, a first electrically conductive type epitaxial layer is formed over a first electrically conductive type base substrate. The impurity concentration of the epitaxial layer is lower than that of the base substrate. A second electrically conductive type first embedded layer and a second electrically conductive type second embedded layer are formed in the epitaxial layer. The second embedded layer is deeper than the first embedded layer, is kept away from the first embedded layer, and has an impurity concentration lower than the first embedded layer. A transistor is further formed in the epitaxial layer.

Semiconductor device having a transistor and first and second embedded layers

The performance of a semiconductor device having a memory element is improved. An insulating film, which is a gate insulating film for a memory element, is formed on a semiconductor substrate, and a gate electrode for the memory element is formed on the insulating film. The insulating film has a first insulating film, a second insulating film thereon, and a third insulating film thereon. The second insulating film is a high-dielectric constant insulator film having a charge accumulating function and contains hafnium, silicon, and oxygen. Each of the first insulating film and the third insulating film has a band gap larger than the band gap of the second insulating film.

Semiconductor device and method of manufacturing the same

A polysilazane film is formed over the main surface of a semiconductor substrate in such a manner that the upper surface level of the polysilazane film buried in a trench of 0.2 &#x3bc;m or less in width becomes higher than that of a pad insulating film and the upper surface level of the polysilazane film buried in a trench of 1.0 &#x3bc;m or more in width becomes lower than that of the pad insulating film. Then, heat treatment is conducted at 300&#xb0; C. or more to convert the polysilazane film into a first buried film made of silicon oxide (SiO) and remove a void in the upper portion of the narrower trench.

Method of manufacturing semiconductor device

To improve productivity and performance of a CMISFET including a high-dielectric-constant gate insulating film and a metal gate electrode. An Hf-containing insulating film for a gate insulating film is formed over the main surface of a semiconductor substrate. A metal nitride film is formed on the insulating film. The metal nitride film in an nMIS formation region where an n-channel MISFET is to be formed is selectively removed by wet etching using a photoresist pattern on the metal nitride films a mask. Then, a threshold adjustment film containing a rare-earth element is formed. The Hf-containing insulating film in the nMIS formation region reacts with the threshold adjustment film by heat treatment. The Hf-containing insulating film in a pMIS formation region where a p-channel MISFET is to be formed does not react with the threshold adjustment film because of the existence of the metal nitride film. Then, after removing the unreacted threshold adjustment film and the metal nitride film, metal gate electrodes are formed in the nMIS formation region and the pMIS formation region.

Manufacturing method of semiconductor device

An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.

Semiconductor device and manufacturing method of the same

A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film. Then, after a silicon oxide film is formed so as to cover the silicon gate electrodes, a surface of the silicon oxide film is polished by CMP, thereby exposing the surface of the silicon gate electrodes. Subsequently, a patterned insulating film is formed on the silicon oxide film. Thereafter, an adhesion film is formed on the silicon oxide film and the insulating film. Then, a nickel film is formed on the adhesion film. Thereafter, a silicide reaction is caused to occur between the silicon gate electrode and the nickel film via the adhesion film.

A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a semiconductor substrate. In the n-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a hafnium silicide film. On the other hand, in the p-type MIS transistor, a gate electrode is formed through a gate insulating film, and the gate electrode is composed of a platinum silicide film. Also, the gate electrodes are formed after the activation annealing (heat treatment) for activating impurities implanted into a source region and a drain region.

Semiconductor device and manufacturing method thereof

A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (HfO) film. Also, the gate electrode of the n channel MIS transistor is composed of an Ni (nickel) silicide film, and the gate electrode of the p channel MIS transistor is composed of a Pt (platinum) film. In this structure, Fermi level pinning of the gate electrodes can be prevented. Therefore, the increase of the threshold voltage of the n channel MIS transistor and the p channel MIS transistor can be inhibited.

The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is composed of a nickel silicide film formed by reacting a silicon film doped with P, As, or Sb with an Ni film, and a gate electrode of a p channel MISFET is composed of a nickel-silicon-germanium film formed by reacting a nondope silicon germanium film with the Ni film. The work function of the gate electrode of the n channel MISFET is controlled by doping P, As, or Sb, and the work function of the gate electrode of the p channel MISFET is controlled by adjusting the Ge concentration.

Semiconductor device having misfet gate electrodes with and without GE or impurity and manufacturing method thereof

In a semiconductor device and production method thereof, a technique is used to prevent film separation of the bottom electrode occurring during a heat treatment process which is carried out to make the bottom electrode closely packed and in the heat treatment process for producing dielectric crystallization. In the production method, a glue layer including an insulator is formed between SiO insulation layer and the inner wall of a concave hole. The SiO layer is located on the Si board , and Si plug and a barrier layer are formed therein. A glue layer is formed on the inner wall of the hole of the SiO insulation layer , and a bottom electrode comprising Ru is formed on the barrier layer and glue layer . Dielectric film comprising BST and a top electrode comprising Ru are laminated sequentially on the bottom electrode , to form a dielectric device with the bottom electrode

Semiconductor device and production method thereof

A sodium-sulfur battery in which sulfur and/or sodium polysulfide are used as cathode active materials, and an electronic conductor, which are arranged in a cathode chamber between a cathode container operating concurrently as a cathode electric collector and a solid electrolyte tube, and a layer, made of a material having a superior corrosion resistance against sulfur and sodium polysulfide, is provided between said solid electrolyte tube and said electronic conductor, wherein the cathode electric collector as the electronic conductor has been improved.

Growing community of inventors

Tokyo, Japan

Masaru Kadoshima