Adv Antest Corporation

Masaru Doi

Shinya Sato

Takashi Hasegawa

Tatsuya Yamada

Kouichi Tanaka

Satoshi Sudou

Takeo Miura

Shinya Satou

Kazuhiro Shibano

Satoshi Kameda

A test apparatus includes: a test executing section executing a test on the device under test; a fail memory storing a test result outputted by the test executing section, the fail memory implementing an interleave technology for interleaving accesses to a plurality of banks; a buffer memory storing the test result transferred from the fail memory and transfers at least part of the test result to a cache memory, the buffer memory being either a memory not implementing the interleave technology or a memory implementing the interleave technology but having a smaller number of banks than the fail memory; the cache memory storing the at least part of the test result transferred from the buffer memory, the cache memory allowing random access in shorter time than the buffer memory does; and an analysis section analyzing the test result stored in the cache memory.

Test apparatus and test method

Provided is a test apparatus having a bad block memory for storing a plurality of pieces of fail information in association with blocks of a memory under test, each piece of fail information indicating whether there is a defect in the associated block. The test apparatus writes a test data sequence to a page under test of the memory under test, reads the test data sequence written to the page under test, and compares the read data sequence to the written data sequence. The test apparatus includes an allocation register that stores allocation information for setting which of the plurality of fail conditions for judging whether there is a defect in the page under test are allocated to the plurality of pieces of fail information. The test apparatus detects whether there is a defect corresponding to each of a plurality of fail conditions, outputs the detection result as a fail signal, and updates a plurality of pieces of fail information associated with the block including the page under test using the fail signal corresponding to the allocated fail conditions.

A test apparatus tests a device under test. The test apparatus includes a period generator that generates a rate signal determining a test period according to an operating period of the device under test, a phase comparing section that inputs an operational clock signal for the device under test generated from the device under test and detects a phase difference between the operational clock signal and the rate signal using the rate signal as a standard, a test signal generating section that generates a test signal to be supplied to the device under test in synchronization with the rate signal, a delaying section that delays the test signal in accordance with the phase difference to substantially synchronize the delayed signal with the operational clock signal, and a test signal supplying section that supplies the delayed test signal to the device under test.

Test apparatus for regulating a test signal supplied to a device under test and method thereof

A test apparatus that tests a plurality of device under tests includes: a common pattern generating section that generates a common pattern being the pattern of a test signal common to the plurality of device under tests; an additional pattern storage section that previously stores therein an additional pattern to be added to the common pattern; and an each pattern adding section that reads the additional pattern for each of the device under tests based on a result signal outputted from the device under test and provides the additional pattern added with the common pattern to the device under test.

Test apparatus that tests a plurality of devices under test having plural memory cells and test method therefor

There is provided a detection apparatus including a transition point detecting unit operable to receive the output signal to detect the point of transition, a timing comparing unit operable to detect the signal level of the output signal in front of or behind the point of transition in the output signal, and a correction unit operable to compensate the timing of the point of transition detected from the transition point detecting unit based on the signal level of the output signal detected from the timing comparing unit.

Detection apparatus, detection method, and program

There is provided a test apparatus for testing a memory under test that includes therein a plurality of blocks and one or more repairing columns. The test apparatus includes a testing section, a flag memory that stores thereon a flag indicating whether each column is defective, a counter memory that stores thereon the number of defective blocks in association with each column, a failure writing section that writes a flag indicating that a column is defective into the flag memory under a condition that one of the following conditions is satisfied: when a test result indicates that the column is defective; and when a flag stored on the flag memory in association with the column indicates that the column is defective, a counting section that increments the number of defective blocks stored on the counter memory in association with the column under a condition that the test result indicates that the column is defective and the flag indicating that the column is defective is not stored on the flag memory in association with the column, and a selecting section that selects columns to be replaced with the repairing columns based on the number of defective blocks stored in association with each column.

Test apparatus and selection apparatus

A multi-strobe generation apparatus for generating a multi-strobe has a plurality of strobes. The multi-strobe generation apparatus includes a shift clock generating section which outputs a shift clock generated by dividing a reference clock at a timing at which each strobe is generated, a strobe generating section for generating the multi-strobe corresponding to each leading or trailing edge of the reference clock, and an adjustment section for adjusting timing at which the strobe generating section generates each strobe based on the shift clock.

Multi-strobe generation apparatus, test apparatus and adjustment method

A multi-strobe apparatus for generating multi-strobe having a plurality of strobes is provided, wherein the multi-strobe apparatus includes a clock generating unit which is able to generate a signal for adjustment at a timing at which each of the plurality of strobes should be generated; a strobe generating circuit for generating the plurality of strobes; and an adjusting module for adjusting a timing of the strobe generating circuit's generating each of the strobes on the basis of the signal for adjustment.

Multi-strobe apparatus, testing apparatus, and adjusting method

A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory unit for storing the test result of said memory-under-test. The fail memory unit includes a write time measuring section for measuring a write time required for writing said test data per each of said pages, an integrating section for integrating said write time across a plurality of said pages set in advance, and a judging section for judging whether or not said memory-under-test is defect-free by comparing a value integrated by said integrating section with an expected value set in advance. The integrating section further integrates said write time per page group having said predetermined number of pages. The judging section further judges whether or not said page group is defect-free based on an integral value of said write time per said page group.

Testing apparatus and testing method

A phase difference between a timing of rising or falling of the data read from a semiconductor device to be test and a timing of rising or falling of a reference clock outputted synchronized with the data is measured by operating sampling with strobe pulses configured with multi-phase pulses given the phase difference by a small amount in regard to the timing of the data and the timing of the reference clock. In addition, a glitch of the data is detected, and the quality of the semiconductor device to be tested is judged based on the phase difference and/or the glitch.

Apparatus and method for testing semiconductor device

A testing apparatus for performing a setup testing or a hold testing on a device under test ('DUT') storing a given data signal according to a given clock signal is provided, wherein the testing apparatus includes a timing generating unit for generating sequentially a plurality of timing signals having different timings during the setup testing or the hold testing on the basis of a fist offset value given before starting the setup testing or the hold testing; a pattern generating unit for generating the clock signal and the data signal; a pattern formatting unit for shifting the phase of the data signal with respect to the clock signal sequentially according to the timing signals sequentially generated and providing the DUT with the clock signal and the phase-shifted data signal sequentially; and a determining module for acquiring a setup time or a hold time of the DUT on the basis of storage data which are the data signals stored by the DUT.

Testing apparatus and a testing method

There is provided a timing generator generating a timing signal of a predetermined period. The timing generator includes a set/reset latch, a set unit supplying the set signal, and a reset unit supplying the reset signal, in which the set unit includes: a first variable delay circuit that delays a given reference clock to output a first set signal; a second variable delay circuit that delays the given reference clock to output a second set signal having a phase different from the first set signal; an OR circuit that computes a logical sum of the first set signal and the second set signal to generate the set signal; and a third variable delay circuit that delays the set signal output from the OR circuit to adjust a skew between the set signal and the reset signal.

Timing generator, test apparatus and skew adjusting method

A method for calibrating a timing clock is provided. The method includes the steps of calibrating a shift amount of an edge of a shift clock by using a period of the timing clock as a reference by detecting an edge of the timing clock more than once while changing the shift amount of the edge of the shift clock; shifting and generating the edge of the shift clock by a predetermined shift amount by the calibrated shift clock generating section; and calibrating a required delay amount for delaying the timing clock by time corresponding to the predetermined shift amount by detecting the edge of the shift clock shifted by the predetermined amount while changing a delay amount of the timing clock.

Method for calibrating timing clock

A timing generator includes a reference clock generating unit for outputting a reference clock at a predetermined time interval, a first variable delay circuit unit for receiving the reference clock and outputting a first delay signal which results from delaying the reference clock, a second variable delay circuit unit for receiving the reference clock and outputting a second delay signal which results from delaying the reference clock, a delay control unit for controlling delay amounts of the first and second variable delay circuit units, and a timing generating unit for generating the timing signal based on the first and second delay signals, wherein the first and second delay control units increase or decrease the delay amounts of the first and second variable delay circuit units to be increased or decreased whenever the reference clock generating unit generates the reference clock.

Timing generator and test apparatus

A test apparatus for testing an electronic device includes a pattern generating unit for generating a test pattern to test the electronic device, a reference clock generating unit for generating a reference clock, a timing generator for generating a timing signal, an output signal sampling circuit for sampling the output signal outputted by the electronic device in response to the test pattern at the timing based on the timing signal generated by the timing generator, wherein the timing generator includes a variable delay circuit unit for receiving, delaying and outputting the reference clock, and a delay control unit for controlling the delay amount of the variable delay circuit unit, and the delay control unit controls the delay amount based on the basic timing data and the variable delay amount which is smaller than the basic timing data.

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Tokyo, Japan

Masaru Doi