Ablic Inc.

Seiko Instruments Inc

Sii Semiconductor Corporation

Masaru Akino

Shinjiro Kato

Yukihiro Imura

Yoshitaka Kimura

Hitomi Sakurai

Takeshi Morita

Yasuo Terui

Shinya Kubota

Hirofumi Harada

Hisashi Hasegawa

Takaaki Hioka

Yukimasa Minami

Koji Tsukagoshi

Hiroyuki Fujita

Sadao Oku

Keiichiro Hayashi

Kaku Igarashi

In a manufacturing step in which a structure of target of screening is formed on a semiconductor substrate in the middle of manufacturing process before a semiconductor device is finished, screening of potential defects of a gate insulating film is performed for each wafer at one time so that the semiconductor device is caused to appear as an initial defective product when the finished semiconductor device is subjected to an electrical characteristic test. Provided are a semiconductor device, and a method of manufacturing a semiconductor device which enables reliable screening of potential defects in a short period of time.

Method of manufacturing a semiconductor device

A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.

Semiconductor device and method of manufacturing a semiconductor device

Method of manufacturing a semiconductor device and semiconductor device

A semiconductor device () includes: a substrate (); a wiring () formed above the substrate (); a titanium nitride film () formed on the wiring (); an oxide film () formed on the titanium nitride film (); a silicon nitride film () formed on the oxide film (); and a pad portion () exposing the wiring (), and formed at a place where a first opening portion () formed in the silicon nitride film () and a second opening portion () formed in the titanium nitride film () overlap with each other in plan view, and being inside a third opening portion () formed in the oxide film () in plan view, wherein the silicon nitride film () is formed on top of and in contact with the titanium nitride film () inside the third opening portion () in plan view.

Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.

A semiconductor device includes: a substrate; a wiring formed above the substrate; a titanium nitride film formed on the wiring; an oxide film formed on the titanium nitride film; a silicon nitride film formed on the oxide film; and a pad portion exposing the wiring, and formed at a place where a first opening portion formed in the silicon nitride film and a second opening portion formed in the titanium nitride film overlap with each other in plan view, and being inside a third opening portion formed in the oxide film in plan view, wherein the silicon nitride film is formed on top of and in contact with the titanium nitride film inside the third opening portion in plan view.

In a Hall sensor in which a Hall element and elements serving as heat sources out of components of a circuit for driving the Hall element are arranged close to each other on a silicon substrate, two directions of control currents by spinning current for the Hall element are selected in a vector manner based on signals from temperature sensors arranged close to a periphery of the Hall element, thereby enabling the elimination of a magnetic offset caused by heat generation of the heat sources.

Hall sensor and compensation method for offset caused by temperature distribution in hall sensor

A corrosion-resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous insulating film so that, when laser light irradiated from a rear surface of a semiconductor substrate is collected at selected fuse elements, the fuse elements generate heat, expand, and rupture. An array of intersecting metal lines forming windows is disposed over the fuse elements to permit rapid expansion of the fuse elements when irradiated with the laser light. A silicon nitride film having a uniform thickness is formed on a front surface of the semiconductor device to prevent entry of moisture.

Semiconductor device having fuse element

A corrosion resistant semiconductor device includes fuse elements that can be cut by laser light. An upper portion of the fuse elements is covered with a porous insulating film so that, when laser light irradiated from a rear surface of a semiconductor substrate is collected at selected fuse elements, the fuse elements generate heat, expand, and rupture. A metal lattice having a plurality of windows is disposed over the fuse elements to permit rapid expansion of the fuse elements when irradiated with the laser light. Alternatively, a metal array having a plurality of independent light-shielding portions may be disposed over the fuse elements to prevent the laser light from adversely affecting circuitry on the front surface side of the semiconductor device.

Semiconductor device having a fuse element

A semiconductor device manufacturing apparatus for encapsulating with a resin a semiconductor chip includes upper and lower molds configured to receive therebetween a lead frame on which the semiconductor chip is mounted. A positioning pin provided to the lower mold is configured to be received by a positioning hole provided in the lead frame. Ejector pins provided in proximity to the positioning pin are arranged so as to be symmetrical with respect to the positioning pin.

Semiconductor manufacturing apparatus

A resin-encapsulated semiconductor device comprises a semiconductor chip mounted on a die pad. A plurality of leads each having an inner lead and an outer lead are arranged in spaced relation from the die pad with the inner leads facing the die pad. A metal plating layer is formed on top surfaces of the inner leads, and the inner leads are connected by metal wires to the semiconductor chip. An encapsulation resin encapsulates the semiconductor chip, die pad, metal wires and inner leads leaving the outer leads exposed. The outer edge of the metal plating layer coincides with the outer surface of the encapsulation resin and with the outer edge of the metal plating layer.

Method of manufacturing resin-encapsulated semiconductor device, and lead frame

A semiconductor resistor circuit has resistor elements of a polycrystalline silicon thin film formed on an insulating film deposited on a semiconductor substrate. A high stress insulating film is formed on and covers the resistor elements and the insulating film exposed between the resistor elements. Metal wirings cover upper portions of the resistor elements. The high stress insulating film has a membrane stress that is higher than that of the metal wirings.

Semiconductor device

Provided is a semiconductor device including a package having a hollow portion, which can meet the need of reduction in size and thickness. The semiconductor device includes: a resin molded member () including a hollow portion () having an inner bottom surface on which a semiconductor chip () is mounted, a surrounding portion () that surrounds the hollow portion (), and a bottom surface portion (); an inner lead (); and an outer lead () exposed from the resin molded member (). The inner lead buried in the molded member () includes an L-shaped lead extending portion having a through hole formed therethrough.

A semiconductor device manufacturing apparatus for encapsulating with a resin a semiconductor chip. A lead frame on which the semiconductor chip is mounted is provided between an upper mold and a lower mold. A tapered positioning pin is provided to the lower mold and includes a columnar portion having an outer diameter larger than an inner diameter of a positioning hole provided at an upper surface of the lead frame and configured to receive the columnar portion of the tapered positioning pin. Ejector pins are disposed in proximity to the tapered positioning pin at a distance determined by a thickness of the lead frame. The ejector pins are arranged so as to be symmetrical with respect to the tapered positioning pin.

Growing community of inventors

Chiba, Japan

Masaru Akino