Mitsubishi Electric Corporation

Masaomi Tsuru

Akihito Hirai

Koji Tsutsumi

Moriyasu Miyazaki

Sho Ikeda

Kenji Kawakami

Toshiyuki Tanaka

Mitsuhiro Shimozawa

Wataru Yamamoto

Yukihiro Homma

Takanobu Fujiwara

Shinya Yokomizo

Kengo Kawasaki

Atsushi Yamamoto

Hidetada Tokioka

Tadashi Takagi

Hidenori Ishibashi

Masatake Hangai

Kazuhiro Miyamoto

Kenichi Tajima

Morishige Hieda

Kiyoshi Ishida

Shinnosuke Soda

Yusuke Kitsukawa

Tamotsu Nishino

Yukinobu Tarui

Eigo Kuwata

Eiji Taniguchi

Hiroyuki Mizutani

Kenichi Miyaguchi

Takayuki Morioka

Hideharu Yoshioka

Kazuhiro Nishida

Hiroyuki Aoyama

Tatsuya Hagiwara

Yasutoshi Yashiki

Masafumi Nakane

Yoshiaki Morino

Jun Shimokawatoko

Satoshi Hamano

Maho Utsumi

There is provided an active phased array antenna in which power to an Si wafer is separated from power to compound semiconductor chips. An active phased array antenna is an active phased array antenna including a substrate having a plurality of antenna elements; a pseudo wafer containing a group of semiconductor chips including a plurality of semiconductor chips made of compound semiconductors; and a silicon wafer made of silicon, the substrate, the pseudo wafer, and the silicon wafer being stacked on top of each other in this order, and the pseudo wafer includes first feeders for supplying power to the group of semiconductor chips from the substrate; and a second feeder for supplying power to the silicon wafer from the substrate, the second feeder passing through the pseudo wafer in a thickness direction of the pseudo wafer.

Active phased array antenna comprising a pseudo wafer including multiple feeders

A first phase shift circuit amplifies, when a first signal, a second signal having a phase difference of 90 degrees from the first signal, a third signal having a phase difference of 180 degrees from the first signal, and a fourth signal having a phase difference of 270 degrees from the first signal are output from a 90-degree distributor that distributes an input signal, each of any three signals from among the first signal to the fourth signal. A second phase shift circuit amplifies each of any two signals of any three signals and one signal that is not amplified by the first phase shift circuit from among the first signal to the fourth signal. One or more phase shift circuits of the first phase shift circuit and the second phase shift circuit each include a compensation circuit that compensates for a phase error of the synthesized signal.

Phase shifter and antenna device

A directional coupler is configured so as to include: a resistive element in which one end thereof is connected to a first terminal and the other end is connected to a second terminal; a first amplifier circuit for outputting either a current directly proportional to a first voltage applied to the one end of the resistive element or a current directly proportional to a second voltage applied to the other end of the resistive element; a second amplifier circuit for outputting a first current which is directly proportional to the voltage difference between the first voltage applied to the one end of the resistive element and the second voltage applied to the other end of the resistive element and whose polarity is different from that of the current outputted from the first amplifier circuit when a signal is flowing from the first terminal to the second terminal, and for outputting a second current which is directly proportional to the voltage difference between the first voltage and the second voltage and whose polarity is identical to that of the current outputted from the first amplifier circuit when a signal is flowing from the second terminal to the first terminal; and a first adder circuit for outputting either a signal having a voltage value directly proportional to a current which is the sum total of the current outputted from the first amplifier circuit and the first current or a signal having a voltage value directly proportional to a current which is the sum total of the current outputted from the first amplifier circuit and the second current to a third terminal.

Directional coupler and semiconductor chip

A phase-variable frequency multiplier includes: a 90-degree divider for dividing an input signal into an I-signal and a Q-signal; an amplitude setting circuit for distributing each of the I-signal and the Q-signal to two paths, setting amplitudes of two of four signals including the two distributed I-signals and the two distributed Q-signals depending on a phase shift amount of the input signal, and outputting as set signals, the four signals including the signals with the set amplitudes; a first mixer for multiplying one of the two I-signals included in the set signals by one of the two Q-signals included in the set signals to generate a first signal having a frequency being twice the frequency of the input signal; a second mixer for multiplying the other of the two I-signals included in the set signals by the other of the two Q-signals included in the set signals to generate a second signal with an amplitude ratio with respect to the first signal, being a tangent or a reciprocal of a tangent of the phase shift amount and with a frequency being twice the frequency of the input signal; and a 90-degree combiner for applying a phase difference of 90 degrees between the first signal and the second signal, and combining the first signal having the phase difference of 90 degrees from the second signal with the second signal.

Phase-variable frequency multiplier and antenna device

A phase detector includes: a phase shift circuit to phase-shift a first positive-phase signal included in a first differential signal and a first negative-phase signal included in the first differential signal, and phase-shift a second positive-phase signal included in a second differential signal and a second negative-phase signal included in the second differential signal; a multiplication circuit to perform multiplication of two signals for all combinations of the first positive-phase signal and the first negative-phase signal with the phase-shifted second positive-phase signal and the phase-shifted second negative-phase signal, and perform multiplication of two signals for all combinations of the phase-shifted first positive-phase signal and the phase-shifted first negative-phase signal with the second positive-phase signal and the second negative-phase signal; and a phase difference calculating circuit to calculate a phase difference between the first differential signal and the second differential signal using multiplication signals of the multiplication circuit.

Phase detector

A third signal having a phase intermediate between a first signal based on a reference signal and a second signal with a phase shifted by an element of a previous stage is generated, a signal obtained by shifting the phase of the third signal by a first phase shill amount is output as a second signal to an element of a subsequent stage, a phase difference between the third signal and a fourth signal obtained by shifting the phase of a first signal output from the element of the subsequent stage by the first phase shift amount is detected, and the first phase shift amount is controlled on the basis of the detected phase difference.

Phase synchronization device

A delay synchronization circuit includes a pulse synthesizing circuit to generate a synthesized signal including a first pulse signal synchronized with a reference signal and a second pulse signal synchronized a feedback signal, a VCDL to delay the synthesized signal g and output a delayed synthesized signal, a pulse separation circuit to generate a first separation signal synchronized with a first pulse signal included in the delayed synthesized signal and generate a second separation signal synchronized with a second pulse signal included in the delayed synthesized signal, a circulator to output a first separation signal to a clock reception circuit and then output the first separation signal returned from the clock reception circuit to the pulse synthesizing circuit as the feedback signal, and a delay-amount control circuit to control a delay amount of the delayed synthesized signal according to a phase difference between the reference signal and the second separation signal.

Delay synchronization circuit, clock transmission circuit, and clock transmission and reception circuit

A mixer includes a first unit mixer, a second unit mixer, a third unit mixer, and a fourth unit mixer that have the same configuration and a first combiner, a second combiner, and a third combiner that have the same configuration. The first to the fourth unit mixers each include a differential RF signal terminal. Output of the first unit mixer and output of the second unit mixer are combined by the second combiner. Output of the third unit mixer and output of the fourth unit mixer are combined by the third combiner. Output of the second combiner and output of the third combiner are combined by the first combiner. The output of the third unit mixer is input to the third combiner with the polarity being determined.

Mixer

A first switch is connected in parallel with a circuit element. A second switch is connected in series with a parallel circuit constituted by the circuit element and the first switch. The first switch and the second switch alternately perform on-off operation.

Switching circuit and variable attenuator

In a time-to-digital converter, a digital signal outputted by a phase information generator is inputted to each of the D terminals of first through Nth (N is a natural number equal to or greater than 2) D-type flip-flop circuits in a first flip-flop group, each of the D terminals is connected to one end of a first delay element, the C terminal of the first D-type flip-flop circuit is connected to another end of the first delay element, the other end of the first delay element is connected to an input terminal, and, when N, the number of flip-flop circuits in the first flip-flop group, is equal to or greater than 3, for each J a natural number from 2 to N&#x2212;1, C terminal of the (J+1)th D-type flip-flop circuit is connected to one end of the Jth delay element and one end of the (J&#x2212;1)th delay element is connected to the other end of the Jth delay element.

Time-to-digital converter

A rectenna controller connected to a rectenna that receives radio frequency power and converts the radio frequency power into direct current power, the rectenna controller controlling the direct current power received from the rectenna and supplying the controlled direct current power to a load, the rectenna controller including: an input terminal receiving the direct current power converted by the rectenna; an output terminal supplying the controlled direct current power to the load; a first switching element disposed in a current path connecting the input terminal to the output terminal; and a controller controlling the first switching element, wherein when the controller does not operate, the first switching element becomes conducting to render the current path conductive.

Rectenna controller and rectenna apparatus including the same

A first phase shift circuit () converts impedance to achieve impedance matching between a third terminal () of a 90-degree hybrid circuit () and a first terminal () of a first nonlinear element (), and shifts a phase of a radio wave by 180 degrees, and a second phase shift circuit () converts impedance to achieve impedance matching between a fourth terminal () of the 90-degree hybrid circuit () and a first terminal () of a second nonlinear element (), and shifts a phase of a radio wave by 90 degrees. As a result of this configuration, a conversion loss of radio waves can be reduced.

High frequency mixer

A first resistor to a fourth resistor and a first capacitor to a fourth capacitor are connected together in series in a ring shape. A first output terminal to a fourth output terminal are connected to series connection points between the first resistor to the fourth resistor and the first capacitor to the fourth capacitor, a first input terminal is connected to a series connection point between the fourth capacitor and the first resistor, and a second input terminal is connected to a series connection point between the second capacitor and the third resistor. Furthermore, a fifth resistor is connected between a series connection point between the first capacitor and the second resistor and a series connection point between the third capacitor and the fourth resistor.

Polyphase filter

A phase and amplitude controlled oscillation device is configured in such a manner that a first controller and a second controller control a phase of a combined output wave obtained by a combiner by performing control to shift phases of respective oscillation frequencies of a first oscillator and a second oscillator in the same direction, and control an amplitude of the combined output wave obtained by the combiner by performing control to shift the phases of the respective oscillation frequencies of the first oscillator and the second oscillator in opposite directions.

Phase and amplitude controlled oscillation device

A first input terminal is connected to a point of connection of a drain terminal of a first transistor and a gate terminal of a fourth transistor. A second input terminal is connected to a point of connection of a drain terminal of a third transistor and a gate terminal of a second transistor. One of first through fourth output terminals to is connected to a source terminal of each of the first through fourth transistors to. A gate terminal of the first transistor and a drain terminal of the second transistor are connected, and a gate terminal of the third transistor and a drain terminal of the fourth transistor are connected.

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Tokyo, Japan

Masaomi Tsuru