Matsushita Electric Industrial Co., Ltd.

Masaomi Toyama

Shiro Dosho

Naoshi Yanagisawa

Keijiro Umehara

Toru Iwata

Shiro Sakiyama

Takashi Morie

Masahiro Fukui

Takefumi Yoshikawa

Hitoshi Kobayashi

Norihide Kinugasa

Ryoichi Suzuki

An analog circuit automatic calibration system for calibrating an object circuit that is an analog circuit having a characteristic changing with an input set value. The system includes: a set value storage section for storing a value and outputting the value to the object circuit as the set value; a characteristic detection section for detecting the characteristic of the object circuit; a first characteristic change section for determining the set value so that the characteristic of the object circuit is optimized; a second characteristic change section for updating the set value so that the characteristic of the object circuit is maintained, using an algorithm different from that used in the first characteristic change section; and a selector for selecting either one of the outputs of the first and second characteristic sections to enable the selected one to be stored in the set value storage section.

Analog circuit automatic calibration system

The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means () for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element () included in the first filtering means () for allowing a first current to flow in accordance with the first voltage; current generating means () for generating a second current at a given rate to the first current; second filtering means () for accepting, as an input, the second current and outputting a second voltage; and adding means () for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit

In order to correct the duty cycle of a given clock signal to produce a clock signal with a 50% duty cycle, a duty cycle correction circuit includes a delay unit for delaying a first clock signal to output a second clock signal and a clock-signal output unit. The clock-signal output unit includes two transistors which use the first and second clock signals as the inputs of respective gates and an inverter circuit for inverting a signal output from a common drain of the transistors to output a third clock signal. The delay unit delays the first clock signal so that the first clock signal falling appears at a timing at which the duty cycle thereof becomes 50%. The two transistors in the clock-signal output unit output, as the third clock signal, a ground voltage and a source voltage as the signal from the common drain in response to the rising of the first clock signal and the falling of the second clock signal, respectively.

Duty cycle correction circuit

In a front end that has a filter circuit and is used for a communication system having an asymmetric communication channel in which upstream and downstream data rates are different, a filter circuit for received signals, which is for filtering received signals, and a filter circuit for transmitted signals, which is for filtering transmitted signals, are provided. The filter circuit for received signals has an amplifier block including a plurality of amplifiers, a capacitor block including a plurality of capacitors and being connected to the plurality of amplifiers included in the amplifier block, and a first and a second resistor blocks each including a plurality of resistors. Either one of the first or the second resistor block is selectively switched so as to be connected to the amplifier block by a resistor block-switching circuit. The circuit scale is reduced since only one amplifier block and one capacitor block are commonly used for two kinds of filter circuits.

Filter circuit, front end of communication system including the filter circuit, and communication device including the same

A semiconductor integrated circuit includes a plurality of units. Each of the units includes a power supply pad, a function circuit, and a power supply control circuit. The plurality of units each have a first state in which the function circuit is in an operating state by the power supply pad being at a prescribed operating potential and a second state in which the function circuit is in a non-operating state by the power supply pad being at a prescribed non-operating potential. The power supply control circuit includes a switching circuit for connecting the power supply pad to the prescribed non-operating potential. The power supply control circuit in each of the plurality of units closes the switching circuit when at least one of the other units is in the first state and opens the switching circuit otherwise.

Semiconductor integrated circuit

A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width.

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Osaka, Japan

Masaomi Toyama