Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Murata Manufacturing Co., Ltd.

Masao Yamane

Atsushi Kurokawa

Tetsuaki Adachi

Hitoshi Akamine

Masashi Suzuki

Kazuhiro Mochizuki

Hiroyuki Takazawa

Susumu Takahashi

Tomonori Tanoue

Yasushi Shigeno

Yoshinori Imamura

Shinya Osakabe

Eigo Tange

Shigeo Goto

Toshiyuki Usagawa

Tomoyoshi Mishima

Kenji Hiruma

Katsuhiko Mitani

Masahiko Kawata

Satoshi Tanaka

Yasunari Umemoto

Hideyuki Ono

Shinichiro Takatani

Masayoshi Kobayashi

Isao Ohbu

Makoto Morioka

Chushiro Kusano

Mitsuhiro Mori

Makoto Kudo

Takuma Tanimoto

Akishige Nakajima

Tatsuto Okamoto

Taro Kitayama

Yasuo Ohsone

The present invention miniaturizes a HEMT element used as a switching element in a radio frequency module. A single gate electrodeis formed in an active region defined by an element separation portionon a main surface of a substratecomprising GaAs. The gate electrodeis patterned so as to extend in the vertical direction of the page surface between source electrodesand drain electrodes, and to extend in left and right directions at other portions. Thus, the ratio of the gate electrodedisposed outside the active region is reduced, and the area of a gate padA is reduced.

Semiconductor device

The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode terminals constitute a second transistor portion. The semiconductor device is quadrangular.

A bipolar transistor having enhanced characteristics is fabricated by etching a base mesa, which is formed below an emitter mesa (upper emitter layer) and a base electrode, so as to have jut regions on the edges of its generally rectangular region. A mask film, e.g., insulating film, is formed to cover the rectangular region and jut regions, and the base layer is etched by use of the insulating film as a mask to form a base mesa. Consequently, abnormal etching can be prevented from occurring along the base electrode and emitter mesa on the edges of the area where the base electrode and emitter mesa confront each other, and an increase in resistance between the base layer and the emitter layer can be prevented, whereby the bipolar transistor can have enhanced characteristics.

Bipolar transistor and a method of manufacturing the same

The invention is directed to improve resistance to destruction of a semiconductor device. A protection circuit having a plurality of bipolar transistors which are Darlington connected between outputs (collector and emitter) of an amplification circuit of a high output is electrically connected in parallel with the amplification circuit. The amplification circuit has a plurality of unit HBTs (Heterojunction Bipolar Transistors) which are connected in parallel with each other. The protection circuit has a two-stage configuration including a first group of a protection circuit having a plurality of bipolar transistors Qto Qand a second group of a protection circuit having a plurality of bipolar transistors.

Semiconductor protection device

A power amplifier system has a high frequency power amplifier circuit section employing source-grounded enhancement type n-channel MESFETs for receiving a drain bias voltage and a gate bias voltage of zero volts or positive low potentials supplied from a unipolar power supply, and amplifying a superposed input signal therewith to output an amplified signal indicative of a change in drain currents. An output matching circuit section applies impedance matching to the amplified signal and outputs the resultant signal. A gate bias voltage circuit section supplies a gate bias voltage to the high frequency power amplifier circuit. When a forward direct current gate voltage is applied to a gate terminal with a source terminal coupled to ground, the DC gate voltage becomes greater than or equal to 0.65 volts, the DC gate voltage causing a gate current value per gate width of 100 micrometers to exceed 100 microamperes.

Power amplifier system and mobile communication terminal device

The present invention provides a semiconductor device for high frequency application having a high breakdown voltage and the method of manufacturing thereof. A region including a first conductivity type high impurity concentration semiconductor and a region including a first conductivity type low impurity concentration semiconductor are provided from an ohmic layer side at the side far from a semiconductor substrate of the end surface of a barrier layer opposite the semiconductor substrate and between the ohmic layer and a gate electrode. The sheet impurity concentration of the region including a first conductivity type low impurity concentration semiconductor is set to be lower than that between the bottom surface of the gate electrode at the side of the semiconductor substrate and the end surface of the channel layer opposite the semiconductor substrate. The sheet impurity concentration of the region including a first conductivity type high impurity concentration semiconductor is set to be higher than that of the region including a first conductivity type low impurity concentration semiconductor.

Compound semiconductor having a doped layer between the gate and an ohmic contact of an active region

Multiple transistors having a common gate pad between first group of drains and second group of drains

A bipolar transistor device with a large current capacity is formed by connecting a plurality of transistor elements to each other in parallel, each transistor element having a collector layer, a base layer, and an emitter layer formed respectively in a semiconductor substrate. In the bipolar transistor device, the base layers of a plurality of the transistor elements are extended in parallel to each other and those base layers are separated from each other. In each separated base layer, a first base electrode is formed on a part of the base layer which is separated from an emitter junction with the emitter layer, and a second base electrode is formed on another portion of the base layer closer to the emitter junction than the first base electrode. To dispose the base electrodes of a plurality of the transistor elements in parallel to each other, a base wiring is connected to the first base electrodes of those elements electrically. Consequently, a ballast resistor that causes no variation in the resistance value can be connected to each of a plurality of the transistor elements.

Semiconductor device and method for fabricating the same

Power amplification system and mobile radio communication terminal

Growing community of inventors

Takasaki, Japan

Masao Yamane