Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Matshushita Electric Industrial Co., Ltd.

Masao Uchida

Osamu Kusumoto

Makoto Kitabatake

Kunimasa Takahashi

Kenya Yamashita

Ryoko Miyanaga

Nobuyuki Horikawa

Masashi Hayashi

Toshiya Yokogawa

Koichi Hashimoto

Masahiko Niwayama

Koutarou Tanaka

Atsushi Ohoka

Shun Kazama

Kazuhiro Adachi

Takashi Hasegawa

Masatoshi Kitagawa

Hiroyoshi Tanaka

Chiaki Kudou

Tsuneo Mitsuyu

Tsutomu Kiyosawa

Koichi Kotera

Akihisa Yoshida

Kazuyuki Sawada

Kouichi Saitou

Kazuya Utsunomiya

Masahiro Hagio

Hideki Nakata

Yuki Ueda

Takeshi Uenoyama

Keiji Akamatsu

Yasuyuki Yanase

Kazuhiro Kagawa

Yuki Tomita

Takayuki Wakayama

Ryo Ikegami

A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

Silicon carbide semiconductor device

A semiconductor device is provided that includes a temperature sensing function that accurately senses a temperature. The semiconductor device includes a first semiconductor layer on a semiconductor substrate, and a temperature sensor. The temperature sensor includes: a sensing-body region of a second conductivity type that is disposed in the first semiconductor layer; a first region of a first conductivity type, and a second region of the first conductivity type that are arranged in the sensing-body region and are apart from each other; and a third region of the second conductivity type that is in the sensing-body region and is between the first region and the second region. A concentration of a first conductivity type impurity in the temperature-sensing conductive layer is higher than a concentration of a first conductivity type impurity in the drift region.

Semiconductor device having a temperature sensor

A semiconductor device includes a silicon carbide semiconductor layer, a termination region disposed in the silicon carbide semiconductor layer, an insulating film covering part of the termination region, an electrode disposed on the silicon carbide semiconductor layer, a seal ring disposed on remaining part of the termination region and surrounding the electrode, and a passivation film covering the insulating film and the seal ring. Assuming that an outer peripheral end of the seal ring and an outer peripheral end of the passivation film have distance L2 at a side of the silicon carbide semiconductor layer, the outer peripheral end of the seal ring and the outer peripheral end of the passivation film have distance L1 at a corner, and the outer peripheral end of the passivation film at the corner has radius of curvature R1, L1&#x3e;L2 and R1&#x2265;L2 are satisfied.

Semiconductor device

A silicon carbide semiconductor device includes an upper gate electrode including a gate pad and a gate wiring line, and an upper source electrode including first and second source pads. The gate wiring line includes a gate global wiring line extending to encircle the source pads, and a gate connection wiring line. The upper source electrode includes an outer periphery source wiring line extending to encircle the gate global wiring line, and first and second source connections connecting the outer periphery source wiring line to the first and second source pads, respectively. The gate global wiring line includes a first portion, a second portion, and a third portion. The first portion is split at a first substrate corner and a second substrate corner and lies between the first substrate corner and the second substrate corner.

The silicon carbide semiconductor device includes a plurality of unit cells each having an MISFET structure and provided on a silicon carbide semiconductor substrate. A gate upper electrode disposed adjacent to the plurality of unit cells includes a gate pad and gate global wires. When viewed in plan, gate electrodes do not overlap with the gate pad.

A semiconductor element includes: a semiconductor substrate of a first conduction type; a silicon carbide semiconductor layer of the first conduction type disposed above a principal surface of the semiconductor substrate; a terminal edge region of a second conduction type disposed in the silicon carbide semiconductor layer; an insulating film; a first electrode disposed on the silicon carbide semiconductor layer; and a seal ring surrounding the first electrode. The terminal edge region is disposed to surround part of a surface of the silicon carbide semiconductor layer when viewed in a normal direction of the principal surface of the semiconductor substrate. The terminal edge region includes a guard ring region of the second conduction type, and a terminal edge injection region of the second conduction type. The seal ring is formed on the terminal edge injection region through an opening disposed on the insulating film.

Semiconductor element and method of manufacturing the same

A semiconductor device comprises a semiconductor substrate, a silicon carbide semiconductor layer of a first conductivity type on the semiconductor substrate, at least one ring-shaped region of a second conductivity type in the silicon carbide semiconductor layer, a first insulating film in contact with a part of the silicon carbide semiconductor layer, and a second insulating film which has a relative dielectric constant larger than a relative dielectric constant of the first insulating film and which is in contact with a part of the at least one ring-shaped region. In the semiconductor device, the at least one ring-shaped region is located in a termination region. The termination region surrounds a semiconductor element region when viewed from the direction perpendicular to a principal surface of the semiconductor substrate.

Semiconductor deviceincludes semiconductor, an electric field relaxation structure, at least one surface electrode, passivation layer, and insulating layer. Semiconductor layerhas a predetermined element region. The electric field alleviation structure is disposed on semiconductorat an end of the element region. On semiconductor, surface electrodeis disposed inside the electric field alleviation structure when viewed in a normal direction of semiconductor. Passivation layercovers the electric field alleviation structure and a peripheral portion of at least one surface electrode, and has an opening portion above surface electrode. On surface electrode, insulating layeris disposed inside opening portionso as to be separated from passivation layer. When viewed in the normal direction of semiconductor, insulating layeris disposed so as to surround partial regionof surface electrode

Semiconductor device having an electric field relaxation structure

A semiconductor device includes a semiconductor substrate of a first conductivity type, having a first principal surface and a second principal surface, a silicon carbide semiconductor layer of the first conductivity type, disposed on the first principal surface, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the second principal surface and forming an ohmic junction with the semiconductor substrate. The semiconductor device satisfies 0.13&#x2264;Rc/Rd, where Rc is the contact resistance between the second principal surface and the second electrode at room temperature and Rd is the resistance of the silicon carbide semiconductor layer in a direction normal to the first principal surface at room temperature.

Semiconductor device including semiconductor substrate, silicon carbide semiconductor layer, first electrode and second electrode

A semiconductor device includes a semiconductor substrate, a silicon carbide semiconductor layer disposed on the semiconductor substrate, and a termination region disposed in the silicon carbide semiconductor layer. The termination region has a guard ring region and an FLR region which is disposed to surround the guard ring region while being separated from the guard ring region, the FLR region including a plurality of rings. The termination region includes a sector section, and in the sector section, an inner circumference and an outer circumference of at least one of the plurality of rings and an inner circumference and an outer circumference of the guard ring region have a same first center of curvature, the first center of curvature being positioned inside the inner circumference of the guard ring region, and a radius of curvature of the inner circumference of the guard ring region is 50 &#x3bc;m or less.

In the silicon carbide semiconductor element, a second silicon carbide semiconductor layer that is in contact with the surface of a first silicon carbide semiconductor layer has at least an upper layer including a dopant of a first conductivity type at a high concentration. Above a junction field effect transistor (JFET) region interposed between body regions that are disposed in the first silicon carbide semiconductor layer so as to be spaced from each other, the silicon carbide semiconductor element has a channel removed region, which is a cutout formed by removing a high concentration layer from the front surface side of the second silicon carbide semiconductor layer, the high concentration layer having a higher dopant concentration than at least the dopant concentration of the JFET region. The width of the channel removed region is smaller than that of the JFET region.

Silicon carbide semiconductor element and method for manufacturing the same

A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface, wherein each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer, and each of sides of the polygonal boundary has an angle of 0&#xb0; to 5&#xb0; inclusive relative to &#x3c;11-20&#x3e; direction of crystal orientations of the semiconductor substrate.

Semiconductor device having barrier region and edge termination region enclosing barrier region

A semiconductor device includes a first silicon carbide semiconductor layer, a source including a source pad and a source wiring, a gate including a gate pad and a gate wiring, first unit cells disposed in a first element region, and second unit cells disposed in a second element region. In a plan view, the first and second element regions are adjacent to each other with the gate wiring between the first and second element regions. A first electrode including the gate electrode of each first unit cell is disposed in the first element region and electrically connected to the gate. A second electrode including the gate electrode of each second unit cell is disposed in the second element region and not electrically connected to the gate. The first and second electrodes are separated below the gate wiring.

Semiconductor device including semiconductor substrate, silicon carbide semiconductor layer, unit cells, source, and gate

A semiconductor device includes first and second second-conductivity-type region groups containing multiple second-conductivity-type regions that are disposed on a first silicon carbide semiconductor layer of a first conductivity type, arrayed in parallel following one direction with a space between each other, and first and second electrodes disposed on the first silicon carbide semiconductor layer and forming a Schottky junction with the first silicon carbide semiconductor layer. The first electrode covers a position where a distance from adjacent first and second second-conductivity-type regions included in a first second-conductivity-type region group, and a distance from a third second-conductivity-type region included in a second second-conductivity-type region group and adjacent to the first and second second-conductivity-type regions, are equal. A Schottky barrier between the first electrode and the first silicon carbide semiconductor layer is larger than a Schottky barrier between the second electrode and the first silicon carbide semiconductor layer.

Semiconductor device with first and second electrodes forming schottky junction with silicon carbide semiconductor layer and method of manufacturing the same

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Osaka, Japan

Masao Uchida