Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Masao Takayama

Shiro Dosho

Kazuo Matsukawa

Yosuke Mitani

Takuji Miki

Takashi Morie

Naoya Yosoku

Koji Obata

Kouichi Nagano

Junichi Naka

Shiho Muraki

Naoya Iguchi

It is intended to provide an AD converter capable of increasing its conversion accuracy. An AD converter is equipped with a clock generator which generates a first clock using a second clock and a comparator which includes a comparison circuit for comparing an input signal with a prescribed value in a first period of the first clock and a precharging circuit for precharging, in a second period of the first clock, an internal voltage to a prescribed value for the next comparison operation. The clock generator includes a replica circuit of the precharging circuit of the comparator. In the replica circuit of the precharging circuit, a precharging period from the start to the end of precharging is set as the second period of the first clock.

AD converter and receiving apparatus

An oversampling time-to-digital converter includes an input pulse generation circuit generating two pulse signals, a reference pulse generation circuit generating two pulse signals, a swap circuit swapping two pulse signals, a multiplexer selecting an output of the input pulse generation circuit or the swap circuit, a time-to-current conversion circuit outputting two pulse currents in accordance with an output of the multiplexer, a current mirror circuit whose input and output terminals receive the two pulse currents, an integration circuit integrating a differential current between the pulse current connected to the output terminal of the current mirror circuit and an output current of the current mirror circuit, and a comparison circuit comparing an output signal of the integration circuit to a threshold voltage. An output signal of the comparison circuit is given to the swap circuit as a control signal.

Oversampling time-to-digital converter

A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.

Time-to-digital conversion circuit and time-to-digital converter including the same

An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.

Oversampling A/D converter

A time integrator integrates time axis information represented by a phase difference between two signals. The time integrator includes a pulse generation circuit configured to convert a time difference between edges of two input signals to a difference between pulse widths of two pulse signals, and to output the two pulse signals, a load circuit having load characteristics changed by the two pulse signals, and an oscillation circuit coupled to the load circuit, and having an oscillation frequency changing in accordance with the load characteristics of the load circuit. An output of the oscillation circuit is output as a result of time integration.

Time integrator and &#x394;&#x3a3; time-to-digital converter

A comparator offset correction device opens an open switchand closes a short-circuit switchin offset correction of a comparator. In this state, a controllerallows the comparatorto repeat, more than once, the operation of comparing reference voltagesinput to two input terminals with each other. The filteroutputs a frequency signal obtained by smoothing a plurality of comparison results. Based on the frequency signal from the filter, the controlleroutputs a threshold value control signal to the comparatorso that the ratio of a high-level voltage to a low-level voltage in the results of the comparison in the comparatoris 50%. Thus, even when a current which will be input may differ from a current which is currently input due to, for example, the influence of noise, the threshold value offset amount is normally corrected.

Offset correction device of comparator

An edge detector includes flip-flops receiving phase signals of a ring oscillator, a resetter canceling the reset states of the flip-flops at the edge timing of an input signal, and a logical operator performing a logical operation on output signals of the flip-flops. A phase state detector detects a phase state of the ring oscillator occurring at the edge timing of the input signal based on the output signals of the flip-flops. A time-to-digital converter converts an edge interval between the input signal and an output signal of the logical operator into a digital value. A latch latches a value of a counter counting the number of cycles of an output signal of the ring oscillator, at the edge timing of the input signal. An operator calculates a digital value of a received signal from output signals of the latch, the phase state detector, and the time-to-digital converter.

Time-to-digital converter

An A/D converter having high accuracy and high throughput irrespective of characteristic variations of analog circuits is provided. The A/D converter includes a voltage-to-time converter configured to synchronize with a sampling clock signal and convert an input analog voltage to a time difference between two signals, and a plurality of time-to-digital converters each configured to convert the time difference between the two signals to a digital value. The plurality of time-to-digital converters operate in an interleaved manner.

A/D converter

Two T filters, one of which includes two resistive elements and one capacitive element and the other of which includes two capacitive elements and one resistive element, are inserted in a negative-feedback section of an operational amplifier, and a resistive element and a capacitive element are connected between each of intermediate nodes and a signal input terminal. A resistive element and a capacitive element which are connected to each other in parallel are connected between the signal input terminal and an inverting input terminal of the operational amplifier. With this configuration, overall admittances where elements connected to the corresponding intermediate nodes are in parallel connection are equal to each other.

Resonator, delta-sigma modulator, and wireless communication device

An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n&#x2212;1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n&#x2212;1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.

Integrator, resonator, and oversampling A/D converter

A semiconductor device comprises an overflow detection circuit () which compares an output of at least one integrator in a &#x394;&#x3a3; modulator () with a predetermined value to output an overflow detection signal; an overflow frequency calculation circuit () which calculates an overflow frequency value that is the frequency of the output from the integrator being outside a normal range, based on the overflow detection signal, and outputs the overflow frequency value; an oscillation judgment circuit () which judges whether the &#x394;&#x3a3; modulator () is in the oscillation state or not based on the overflow frequency value; and an oscillation halt circuit which suppresses oscillation of the &#x394;&#x3a3; modulator () when the oscillation judgment circuit () judges that the &#x394;&#x3a3; modulator is in the oscillation state; wherein it is determined whether the output of the integrator is temporarily outside the normal range due to noise or the like or the output of the integrator is outside the normal range due to oscillation, by obtaining the frequency with which the output of the integrator is outside the normal range, and the oscillation of the &#x394;&#x3a3; modulator () is suppressed only when it is oscillated.

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Osaka, Japan

Masao Takayama