Fujitsu Corporation

Spansion Llc.

Elpida Memory, Inc.

Cypress Semiconductor Corporation

Fujitsu Semiconductor Limited

Ps4 Luxco S.a.r.l.

Fujitus Limited

Masao Taguchi

Yoshihiro Takemae

Yasurou Matsuzaki

Takaaki Suzuki

Satoshi Eto

Hiroyoshi Tomita

Hirohiko Mochizuki

Shinya Fujioka

Yoshinori Okajima

Atsushi Hatakeyama

Yasuharu Sato

Kenji Nakagawa

Masao Nakano

Naoharu Shinozaki

Kotoku Sato

Makoto Koga

Hiroshi Yoshioka

Taiji Ema

Tadao Aikawa

Junji Ogawa

Hitoshi Ikeda

Koichi Nishimura

Yukinori Kodama

Makoto Yanagisawa

Miki Yanagawa

Akihiro Funyu

Kazuhiko Sumi

Yuichiro Yanagishita

Kimiaki Satoh

Hideaki Kawai

Seiichiro Yamaguchi

Toshiaki Kawabata

Hiroyuki Tanaka

Toshiya Uchida

Masato Matsumiya

Satoru Asai

Isamu Hanyu

Tamae Haruki

Satoru Sugimoto

Waichirou Fujieda

Takayuki Nagasawa

Kuninori Kawabata

Toshikazu Nakamura

Kenichi Kawasaki

Masato Takita

Ayako Kitamoto

Tatsuya Usuki

Toru Koga

Mitsuhiro Higashiho

Kouji Tsunoda

Hideki Kano

Hiroko Douchi

Terumasa Kitahara

Satoshi Sakurakawa

Takahiro Hatada

Hiroyuki Kobayashi

Akira Ogawa

Takashi Ito

Tsuyoshi Higuchi

Takashi Kato

Naoki Yokoyama

Kenichi Imamura

Nobuo Toyokura

Toyonobu Yamada

Hisatsugu Shirai

Katsuyoshi Kobayashi

Toyomitsu Matsumoto

Tetsuya Endo

Shin-ya Fujioka

Takuo Ito

A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.

Nonvolatile semiconductor memory device and memory system having the same

A resistance changing memory array architecture includes an array of resistance changing memory unit cell arranged in rows and column, wherein at least two adjacent columns share a sense bit line, and a control line individually associated with each column, wherein a current control component within each unit cell along a respective column is coupled to a respective control line. The architecture further includes a plurality of word lines each associated with a respective row, wherein a resistance changing element associated with each unit cell along a respective row is coupled to a respective word line.

Resistive changing memory cell architecture having a select transistor coupled to a resistance changing memory element

At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (&#x2212;3.5 V or 0 V). This configuration eliminates an application of a pulsed voltage to the word line at the time of reading, making it possible to reduce an influence of read disturbance. In addition, even when a voltage in a range from a power source voltage to a ground voltage or a voltage over the power source voltage is required at the time of reading, it becomes a voltage about 1.5 times an absolute value of the power source voltage. Therefore, a voltage step-up circuit having a large number of stages is not required, and as a result, it is possible to achieve a reduced operation time with a low power consumption.

Nonvolatile semiconductor memory device and method of reading data from nonvolatile semiconductor memory device

A resistance changing memory unit cell includes a current control component operably coupled to a bit sense line, and a resistance changing memory element coupled between the current control component and a word line.

Multi-state resistance changing memory with a word line driver for applying a same program voltage to the word line

A semiconductor device that includes: a memory cell array that includes non-volatile memory cells; an area that is contained in the memory cell array and stores area data; a first storage unit that holds data transferred from the memory cell array, and outputs the data; and a control circuit that selects between a primary reading mode for causing the first storage unit to hold the area data transferred from the memory cell array and to output the area data, and a secondary reading mode for causing the first storage unit to hold a plurality of pieces of divisional data formed by dividing the area data and transferred from the memory cell array and to output the divisional data.

Ornand flash memory and method for controlling the same

A memory system is provided forming a switch element having a first side and a second side, forming a cell transistor having a gate terminal, forming a memory cell, having the switch element and the cell transistor, with the gate terminal connected to the second side, connecting a word line and the memory cell at the first side, connecting a bit line and the memory cell, and connecting a reference source and the memory cell.

Memory system with switch element

In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the conductor is an elongated metal body of T-shaped cross-section. In another embodiment, the conductor is a plate-like metal body.

Memory cell array with low resistance common source and high current drivability

In the present method of changing the state of a resistive memory device which is capable of adopting an erased, relatively higher resistance state and a programmed, relatively lower resistance state, the resistive memory device having first and second electrodes and an active layer between the first and second electrodes, an electrical potential is applied across the electrodes and current through the resistive memory device is limited by means of a first current limiting structure to change the resistive memory device from the erased, higher resistance state to the programmed, lower resistance state. Furthermore, an electrical potential is applied across the electrodes and current through the resistive memory device is limited by means of a second current limiting structure to change the resistive memory device from the programmed, lower resistance state to the erased, higher resistance state.

Resistive memory cell array with common plate

A semiconductor device having a register and an information generation circuit can reduce data to be transferred, and consequently save electric power. The register stores first information. The information generation circuit generates, in response to a signal acquired from the an exterior of the device, second information indicating which bits of the first information is to be inverted.

Semiconductor device with circuitry for efficient information exchange

A resistance changing memory unit cell includes a resistance changing memory element coupled to a sense bit line and a diode coupled to the resistance changing memory element.

Non-volatile resistance changing for advanced memory applications

A semiconductor device has: an isolation region formed on a semiconductor substrate and defining a continuous active region including a select transistor region and a direct tunnel element region; a gate insulating film formed on a channel region of the select transistor region; a tunnel insulating film formed on a partial area of the direct tunnel element region and having a thickness different from a thickness of the gate insulating film; a continuous floating gate electrode formed above the gate insulating film and the tunnel insulating film; an inter-electrode insulating film formed on a surface of the floating gate electrode; a control gate electrode facing the floating gate electrode via the inter-electrode insulating film; and a pair of source/drain regions formed on both sides of the channel region of the select transistor region and not overlapping the tunnel insulating film.

Direct tunneling memory with separated transistor and tunnel areas

Growing community of inventors

Kawasaki, Japan

Masao Taguchi