Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Hitachi Chemical Company, Ltd.

Renesas Technology Corp.

Masao Sugiyama

Motoshige Igarashi

Takayuki Sasaki

Atsushi Hiraiwa

Naozumi Morino

Keiichi Higashitani

Hiroshi Yanagita

Toshiaki Ito

Masaya Ozawa

Kazutoshi Oku

Shinichi Watarai

Masatoshi Kimura

Kenji Yoshiyama

Takeshi Fukao

Katsumi Eikyu

Hiroyuki Amishiro

Yoshinori Kondo

Yoshiyuki Kaneko

Takeshi Kitani

Hideyo Haruhana

Masayoshi Hirasawa

Provided herein is a molding material that attains little fluctuation in amount of short fibers and powdery resin among individual products and that allows continuous production without damaging a die. In the step of pouring, slurry is poured onto a slurry diffusion memberfrom above the slurry diffusion member. The slurry diffusion memberextends in an upward direction, and is shaped such that the area of a transverse section taken along a direction orthogonal to the upward direction becomes smaller as the slurry diffusion memberextends in the upward direction. In the step of cleaning, a dispersion medium that is the same as the dispersion medium used in the step of pouring or water is poured onto the slurry diffusion memberfrom above the slurry diffusion memberto cause the short fibers and the powdery resin adhering to a slurry diffusion portionof the slurry diffusion memberto fall down. After that, the dispersion medium is discharged from a cylindrical dieto accumulate the short fibers and the powdery resin in the cylindrical dieto obtain an aggregateof the short fibers and the powdery resin. Then, the aggregateis compressed.

Method of manufacturing molding material, molding die for use in the manufacturing method, and method of manufacturing resin rotator

There is little fluctuation in amount of short fibers among individual products of fiber substrate. No damage is caused to a mold for the fiber substrate. Continuous production of the fiber substrates is possible. A method of manufacturing a fiber substrate includes the steps of: preparing slurry by dispersing short fibers in a dispersion medium; pouring the slurry into a cylindrical mold from above the cylindrical mold, the slurry being directed to a slurry diffusion member disposed in the center of the cylindrical mold and having an upward pointing conical or pyramidal shape; pouring the dispersion medium or water onto the slurry diffusion member from above the slurry diffusion member to cause the short fibers adhering to the slurry diffusion member to fall down, after the step of pouring the slurry; and discharging the dispersion medium from the cylindrical mold to accumulate the short fibers in the cylindrical mold to obtain a fiber aggregate.

Method of manufacturing fiber substrate and method of manufacturing resin rotator

Provided herein is an apparatus of manufacturing a molding material for use in a method of manufacturing a molding material that can prevent a crack from occurring in the molding material. A cylindrical die () is slid downward along an upper hollow compression mold () and a lower hollow compression mold () with a molding material () held between the upper hollow compression mold () and the lower hollow compression mold (). After that, the upper hollow compression mold () is moved upward to relatively move the upper hollow compression mold () and the lower hollow compression mold () away from each other. After a slurry diffusion member () is removed, the molding material () is taken out.

Method and apparatus of manufacturing molding material, and method of manufacturing resin gear

There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Semiconductor device having a plurality of shallow wells

As a method for constituting a pre-metal interlayer insulating film, such method is considered as forming a CVD silicon oxide-based insulating film having good filling properties of a silicon oxide film by ozone TEOS, reflowing the film at high temperatures to planarize it, then stacking a silicon oxide film having good CMP scratch resistance by plasma TEOS, and, further, planarizing it by CMP. However, it was made clear that, in a process for forming a contact hole, crack in the pre-metal interlayer insulating film is exposed in the contact hole, into which barrier metal intrudes to cause short-circuit defects. In the present invention, in the pre-metal process, after forming the ozone TEOS film over an etch stop film, the ozone TEOS film is once etched back so as to expose the etch stop film over a gate structure, and, after that, a plasma TEOS film is formed over the remaining ozone TEOS film, and then the plasma TEOS film is planarized by CMP.

Semiconductor integrated circuit device and a method for manufacturing a semiconductor integrated circuit device

Semiconductor device

A semiconductor device that permits effective use of a region positioned under a positional detection mark or an external electrode, i.e., the region that has not been conventionally utilized may be provided. In a semiconductor device including a lower layer, a shielding film and an upper layer, the lower layer includes at least one selected from the group consisting of a positional detection mark, a quality testing element, and a circuit element. The shielding film is formed on the lower layer and shields an energy beam used for detecting a positional detection mark. The upper layer includes a positional detection mark formed on the shielding film.

Semiconductor device comprising layered positional detection marks and manufacturing method thereof

There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE OF DUAL-GATE CONSTRUCTION, AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY INCLUDING FORMING A REGION OF OVER-LAPPING N-TYPE AND P-TYPE IMPURITIES WITH LOWER RESISTANCE

A semiconductor device having a memory cell region comprising a plurality of memory cells is described, and a stable characteristic is imparted to all the memory cells provided in the memory cell block. Impurities are implanted into a memory cell region of a silicon substrate at predetermined intervals, thus forming a plurality of wells. A resist film used as a mask for implanting impurities has strip-shaped patterns and a broad pattern. Since the strip-shaped patterns located close to the broad pattern are inclined, the characteristics of the wells located in the vicinity of the outer periphery of the memory cell region become unstable. The wells having unstable characteristics are taken as dummy wells which do not affect the function of a semiconductor device.

Semiconductor device having a dummy pattern

Both P type and N type impurities are implanted from a plurality of directions. The tilt angle &thgr; of the implantation direction against the normal of the main surface of a semiconductor substrate is fixed to 10&deg;, and the deflection angle &phgr; is set to such four directions (X, X&plus;90&deg;, X&plus;180&deg;, and X&plus;270&deg;, where X is an arbitrary angle) that projecting components of a vector indicating the implantation direction are opposed to each other on two lines that cross each other at right angles along the main surface of the semiconductor substrate. Thereby, the dependency of the breakdown voltage of element isolation on the direction of a well boundary is suppressed to realize a high breakdown voltage of element isolation in all directions.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device which prevents a short circuit between a gate electrode and a diffusion layer region if a contact hole is shifted from its proper position. A material having an etch selectivity to an interlayer insulation film is formed over the gate electrode to serve as a cover against the formation of a contact hole. A material is not formed over an interconnect line which is required to be exposed to a contact hole.

After formation of a gate electrode and source/drain regions, N ions or O ions are implanted into a predetermined region using a resist mask, and a Ti layer is deposited on the entire face of a substrate. The Ti layer is then silicided in self-alignment by a heat treatment, whereby a high resistivity TixNySiz mixing layer is formed the predetermined region on the gate electrode and the source/drain regions 10, and a low resistivity TiSi.sub.2 layer 12 is formed on another region.

Method of manufacturing a semiconductor device employing salicide

After formation a gate electrode and source/drain regions, N ions or O ions are implanted into a predetermined region using a resist mask, and a Ti layer is deposited on the entire face of a substrate, and then the Ti layer is silicided in self-alignment by a heat treatment, whereby a high resistivity TixNySiz mixing layer is formed the predetermined region on the gate electrode and the source/drain regions 10, and a low resistivity TiSi.sub.2 layer 12 is formed on another region.

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Tokyo, Japan

Masao Sugiyama