Renesas Electronics Corporation

Masao Morimoto

Yasuhisa Shimazaki

Noriaki Maeda

Masanao Yamaoka

Shigenobu Komatsu

Toshiaki Sano

Yasuyuki Okuma

Makoto Yabuuchi

Yuichiro Ishii

Yohei Sawada

Shinji Tanaka

A semiconductor device includes a memory array having a plurality of associative memory cells arranged in a matrix form for storing entries. The memory array is divided into a plurality of memory blocks for sequentially performing a retrieval operation along a column direction, and further includes a plurality of match lines corresponding to the respective memory blocks and provided correspondingly to each memory cell row, a plurality of search lines corresponding to the respective memory blocks and provided correspondingly to each memory cell column, and a plurality of match amplifiers corresponding to the respective memory blocks and provided to the plurality of match lines. The match line provided correspondingly to the preceding memory block is set to become shorter than the match line provided correspondingly to the subsequent memory block. The memory array further includes a timing control unit for controlling timing for driving the search line of the subsequent memory block based on a length of the match line provided correspondingly to the preceding memory block.

Semiconductor device and semiconductor system

The plurality of CAM cells MC are configured to discriminate a match or mismatch between stored data stored in advance and search data. A match line is coupled to a plurality of CAM cells, and has a voltage level controlled based on discrimination results of the plurality of CAM cells. A first transistor and a second transistor are coupled in series between a common match output line and a predetermined power source. The first transistor is controlled to be turned ON or OFF based on a voltage level of the match line, and the second transistor is controlled to be turned ON or OFF by a search enabling signal asserted at the time of a search operation.

Semiconductor device having a contents addressable memory

A content addressable memory includes a plurality of TCAM cells which configure one entry, a first word line coupled to the TCAM cells, a second word line coupled to the TCAM cells and a match line coupled to the TCAM cells and further includes a valid cell which stores a valid bit which indicates validity or invalidity of the entry, a bit line coupled to the valid line and a selection circuit which is coupled to the first word line and the second word line and sets the valid cell to a selected state in accordance with a situation where the first word line or the second word line is set to the selected state.

Content addressable memory

A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

Semiconductor device including memory cell array with transistors disposed in different active regions

A semiconductor device includes a latch circuit receiving a first signal, generated in synchronization with a clock signal, from a pulse generation circuit, and generating a second signal; a first delay circuit receiving the second signal from the latch circuit, and generating a third signal by delaying the second signal; a second delay circuit receiving the third signal from the first delay circuit, and generating a fourth signal by delaying the third signal; and a logic circuit receiving the second and fourth signals from the latch and second delay circuits, respectively, and generating a word line control signal based on one of the second signal and the fourth signal. The latch circuit generates the second signal of a first level based on the first signal, and generates the second signal of a second level, which is different from the first level, based on the third signal.

Multiport memory, memory macro and semiconductor device

A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

Semiconductor integrated circuit device and system

A circuit includes a memory cell array which includes: a plurality of memory cells; a plurality of word lines coupled to the memory cells, respectively, and a plurality of bit lines coupled to the memory cells, an address control circuit which includes: a first latch circuit into which a first address signal is input and from which a first output signal is output; a selection circuit into which a second address signal and the first output signal are input and which selects the first output signal or the second address signal for outputting the first output signal or the second address signal as a second output signal; a second latch circuit into which the second output signal is input and from which a third output signal is output; a decode circuit which decodes the third output signal and outputs a fourth output signal; and a word line drive circuit.

Semiconductor device including memory cell array and power supply region

A multiport memory includes an address control circuit, a memory array, a data input-output circuit and a control circuit and first and second address signals and a clock signal are input through two ports. The address control circuit includes first and second latch circuits, a selection circuit, a decode circuit and a word line drive circuit. The first address signal input through one port is input into the first latch circuit and the second address signal input through the other port is input into the selection circuit. The selection circuit selects one of the first and second address signals, the second latch circuit latches and outputs the selected address signal to the decode circuit. The word line drive circuit drives a word line on the basis of an output signal from the decode circuit.

Growing community of inventors

Tokyo, Japan

Masao Morimoto