Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Communication Systems, Inc.

Hitachi Ome Electronic Co., Ltd.

Hitachi Automotive Engineering Co., Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi, Vlsi Eng. Corp.

Hitachi Ome Electric Co., Ltd.

Masao Mizukami

Yoichi Sato

Isao Hayase

Kouji Masuda

Satoshi Shinagawa

Nobuaki Kitamura

Nobuaki Kanazawa

Yukio Takahashi

Atsuo Kishi

Toshiyuki Ookuma

Kunihiro Ito

Yukio Nakano

Hisanobu Kanamaru

Takahiko Kozaki

Masaru Ito

Kunihiko Takao

Kenichi Kawashima

Kazuo Koide

Atsushi Suginuma

Kosaku Sayo

Akira Tezuka

Toshikazu Ito

Kazuhiro Tsuruoka

Hideo Usui

Toshio Sudo

Kenji Emi

Satoshi Hososaka

Masaaki Ishiguri

Masahiro Moritaka

Junya Kudoh

Keijirou Amano

Takefumi Ohwada

Kiyosi Yamamoto

Signal receiving circuit and digital signal processing system

Write column selection MOSFETs of memory cells MC are coupled with, for example, the earth potential of the circuit. Write column selection signals supplied to these MOSFETs are formed selectively according to the column selection address signal and the write data. Thereby the write column selection MOSFETs of the memory cells MC function as a substantial write means. That is, the write column selection signal lines are used as the data lines at the same time.

Multiplexed multi-write port semiconductor memory

A differential type MOS transmission circuit includes a signal driving circuit and a signal receiving circuit to realize high speed transmission for a short distance transmission between different LSIs, etc. A pair of transmission lines between the signal driving circuit and the signal receiving circuit are driven by a pair of drivers in the signal driving circuit so as to take either one of three states, i.e. one state where both of the lines are in a precharged states and two states where either one of the lines is in a discharged state. A signal driving circuit includes signal generating circuits generating variations in control signals varying pulse-like in response to rise and fall of an input signal to thereby obtain the discharge state. The signal receiving circuit generates an output signal depending on the state of the transmission lines and is constructed of a Schmitt trigger circuit with a hysteresis characteristic, for which an input threshold voltage for output logical values has a level smaller than a potential difference between the precharged level and the discharged level.

Differential type MOS transmission circuit

One paired wiring traveling in parallel to a transmission path of a signal and a transmission path of reference voltage is used, and a terminal end resistor matched with the characteristic impedance is installed, and in a receiving circuit connected thereto, a differential input circuit with offset set to about 1/2 of the terminal end voltage is used, and an output circuit of open drain is used in a transmitting circuit. A high-speed information processing section using such a bus circuit and a low-speed information processing section using a conventional low-speed bus are mutually connected through an interface circuit to construct the system hierarchically.

Signal transmission method, signal transmission circuit and information

A signal transmission system provides stable, fast, long-range transmission. During transmission, a short-width pulse is synchronized with rising and falling edges of a transmission pulse signal. A ternary output signal in a differential shape is produced on the basis of the pulse, and an output signal is transmitted through series resistors via a pair of transmitting wirings. During reception, a reception terminal is provided with terminal resistors corresponding to a characteristic impedance of the transmitting wirings. A signal having passed through one of the transmitting wirings is detected with reference to a signal having passed through the other transmitting wiring. A signal having passed through the other transmitting wiring is detected with reference to the signal having passed through the one transmitting wiring. Additionally, the original pulse signal is restored and reproduced on the basis of the detected signals. The signals to be transmitted through the paired transmitting wirings are bipolar pulses or differential pulses which are generated only at the rising and falling times of the pulse signal to be transmitted. The pulses are given a complementary transmission waveform having a small amplitude divided by the series resistors at the transmission side and the terminal resistors at the reception side. In consideration of the above, and since the signals containing no-DC component can be transmitted, the charging and discharging phenomena of the inter-line capacities and the DC shift can be eliminated to accomplish long-range transmissions at a high speed.

A ternary signal transmission circuit and method

A rate conversion circuit area (8) is provided between a spread gate area (4) which operates in synchronization with a clock signal CLK and a RAM core (7) (macro cell) operating in synchronization with a clock signal (ck) whose frequency is higher than that of the clock signal (CLK). With this arrangement, the single port core is made accessible as a dual port RAM by forming the clock signal (ck) whose frequency is multiplied an optional number of times that of the clock signal (CLK), receiving access data equivalent to a plurality of operating cycles in parallel from the spread gate area during a predetermined unit operating access cycle period in the spread gate area, and serially supplying these to the RAM core 7 during the plurality of operating cycle periods in synchronization with the clock signal (ck).

Semiconductor integrated circuit

A memory array of a static RAM or the like is divided in a word line extending direction to constitute a plurality of sub memory arrays SM0 to SM7, and array selecting signals for selecting the sub memory arrays and sub word line selecting signals for selecting sub word lines are combined to form word line selecting signals selectively. Main word lines M0000 to M0003 for transmitting those word line signals are arranged in parallel with the sub word lines SW000 to SW255. Sub word line drive circuits SWD000 to SWD255 are also coupled to the individual sub word lines for bringing the corresponding sub word lines selectively into selected states by combining at least 2 bits of the word line selecting signals.

Semiconductor storage device

A signal transmission circuit in which a signal is converted into two complementary signals which are outputted from a signal transmission circuit via series resistors. The amplitude of each of the complimentary signals is reduced by the series resistors and terminating resistors provided on a signal receiving side. The signal receiving side shifts the level of the signals which it inputs. The level shifted signals are amplified by a high-input impedance differential amplifying circuit.

Complementary signal transmission circuit with impedance matching

Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state. Prior to a reading operation, the data lines are prechanged to the first power-source voltage level, or ground potential, and the common data line is precharged to a second power-source voltage level, such as the supply voltage of the memory. The memory array is implemented in a semiconductor storage device, such as a static RAM, which is characterized as operating either as a one-port or two-port system and wherein it, furthermore, employs a write amplifier circuit arrangement and a sense amplifier arrangement, such as of the single-ended differential type, wherein the write and sense amplifier arrangements can be disposed either on separate common data lines or on a single common data line.

A semiconductor memory device has a sense amplifier which is constructed with a level shift circuit having an input which senses the change in a data line from an initial precharged level to a level near the vicinity of the supply voltage level which corresponds to data reading amounts from a memory cell during the reading mode of operation of the memory. The level shift circuit, in response to a memory cell reading signals, provides a level shifted outpout to the input terminal of a differential sense amplifier circuit, the level shifted output being in the vicinity of the operating point of the differential sense amplifier circuit. The level shift circuit includes a current amplifier having an output terminal that is formed with a series connecting node of a current amplifying transistor and a current source.

High speed sensor system using a level shift circuit

A semiconductor memory device has a sense amplifier which is constructed with a level shift circuit having an input which senses the change in a data line from an initial precharged level to a level near the vicinity of the supply voltage level which corresponds to data reading amounts from a memory cell during the reading mode of operation of the memory. The level shift circuit, in response to a memory cell reading signals, provides a level shifted output to the input terminal of a differential sense amplifier circuit, the level shifted output being in the vicinity of the operating point of the differential sense amplifier circuit. The level shift circuit includes a current amplifier having an output terminal that is formed with a series connecting node of a current amplifying transistor and a current source.

Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state. Prior to a reading operation, the data lines are precharged to the first power-source voltage level, or ground potential, and the common data line is precharged to a second power-source voltage level, such as the supply voltage of the memory.

Semiconductor storage device with common data line structure

A method of combining a plurality of parts and a structure of a plurality of parts combined by the method, wherein each of the plurality of parts are provided with connecting bores in opposed portions thereof, the plurality of parts are put together in a piled state and a connecting tube is inserted into the connecting bores. An expanding punch is provided for subsequently expanding the connecting tube thereby combining or connecting members to each other.

Method of combining plurality of parts and structure of plurality of

A variable displacement compressor comprises a housing forming a crank chamber, a shaft, expansible chambers including pistons, a swash plate connected to the shaft so as to be smoothly changeable in inclination against the shaft and driven to rotate, a wobble plate rotatable on the swash plate, a rotation preventing mechanism including a shoe member slidable in an axial direction, and a pressure control valve which is provided in a refrigerant passage from a suction port of the compressor to the expansible chamber to control the pressure of refrigerant to be sucked responsive to the suction pressure and both to the suction pressure and to the discharge pressure when the discharge pressure is high. The refrigerant passage has a sharply bent portion for separating lubrication oil from a refrigerant flowing therein and communicates with the crank chamber to discharge blow-by gas therefrom.

Variable displacement wobble plate compressor with capacity control valve

Growing community of inventors

Yokohama, Japan

Masao Mizukami