Fujitsu Corporation

Fujitsu Semiconductor Limited

Spansion Llc.

Jatco Corporation

Fujitsu Microelectronics Limited

Kyushu Fujitsu Electronics Limited

Masao Kumagai

Shinya Udo

Hideto Fukuda

Osamu Kudo

Hiromu Enomoto

Masatoshi Kokubun

Yasushi Yasuda

Akinori Tahara

Takeo Shigihara

Hidekazu Nishizawa

Toru Nakamura

Kazuyoshi Futamura

Yoshio Jimbo

Fumiya Yakabe

Koichiro Kushida

Kimitaka Yoshiyama

Hirofumi Dohgome

Yoshio Jatco Ltd Jimbo

Fumiya Jatco Ltd Yakabe

A control circuit arranged in a power supply including first and second switches to control an output voltage of the power supply. The control circuit includes a first control circuit that switches the first and second switches in a complementary manner in accordance with a comparison result of a first reference voltage and a feedback voltage corresponding to the output voltage of the power supply. A first comparison circuit compares the output voltage or feedback voltage with a second reference value. A second comparison circuit compares a coupling point current flowing through a coupling point between the first and second switches with a third reference value. A second control circuit disables complementary switching of the first and second switches in accordance with an output signal from the first comparison circuit and enables the complementary switching in accordance with an output signal of the second comparison circuit.

Control circuit, electronic device, and method for controlling power supply

A D/A converter for receiving a plurality of divisional voltages and converting a digital signal to an analog voltage with the divisional voltages, the D/A converter includes a selection circuit for receiving the divisional voltages and the digital signal to select one of the divisional voltages. The selection circuit includes a plurality of first switch circuits that are selectively activated in response to the digital signal to select one of the divisional voltages, with each of the first switch circuits being provided with a logic switch function and having an ON resistance when activated, and at least an activated one of the first switch circuits further dividing the selected one of the divisional voltages with the ON resistance. The plurality of switch circuits includes at least one voltage dividing switch circuit used to further divide the selected one of the divisional voltages.

D/A converter

A driver IC for a display that includes a first D/A converter with a 1selection circuit that receives 1image signals and supplies a selected positive divisional voltage to a 1operational amplifier, which supplies a positive pixel voltage by amplifying the selected positive divisional voltage; a 2D/A converter with a 2selection circuit that receives 2image signals and supplies a selected negative divisional voltage to a 2operational amplifier, which supplies a negative pixel voltage by amplifying the selected negative divisional voltage; and a polarity switching switch with 1and 2switches connecting the 1and 2D/A converters respectively, the polarity switching switch being switched to supply each of output terminals corresponding to the 1and 2image signals alternately with the positive and negative pixel voltages every horizontal scan period by activating/inactivating the 1and 2switches in a complementary manner.

Driver IC for display and display including same

A method for strengthening a surface of a metal member. The method includes the following steps in the sequence set forth: (a) coating the surface of the metal member with a carbon-based film having a thickness of not smaller than 0.2 &#x3bc;m; and (b) repeatedly applying a pressing force onto the surface of the film-coated metal member in a condition of maintaining a contact pressure of not lower than 2.5 GPa at the surface of the film-coated metal member.

Surface strengthening method

A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which signals are output and output pads corresponding thereto. The test circuit includes output switches caused to sequentially make connections by a controller in test and interpad switches involved in making connections of the output pads with a test pad by the controller in test. In test, probe needles are brought into contact with the test pad. The output pads are not used in test, and can be arranged at a narrowed pitch. Thus, the chip area can be reduced and are therefore so that the pitch for the output pads can be narrowed and the chip area can be decreased.

Semiconductor device and liquid crystal panel driver device

A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.

Method for driving display and drive circuit for display

A display device includes a plurality of data drivers which are cascade-connected, and prevents variation of the duty ratio of a signal caused by accumulation of errors. In each of the plurality of data drivers: a first input circuit receives a first signal supplied from outside; a second input circuit receives a second signal supplied from outside, in response to the first signal received by the first input circuit; a signal processing circuit performs signal processing based on the second signal received by the second input circuit; a first output circuit inverts the first signal received by the first input circuit, and outputs the inverted first signal; and a second output circuit delays the second signal received by the second input circuit, by a predetermined amount, and outputs the delayed second signal.

Semiconductor device, display device, and signal transmission system

An integrated circuit includes a first signal-inversion switching circuit which receives a signal supplied from an exterior thereof as a first input signal, followed by outputting the first input signal after logic inversion thereof in response to a first state of a switching signal and outputting the first input signal without logic inversion in response to a second state of the switching signal, a signal processing circuit which performs signal processing based on the output of the first signal-inversion switching circuit, and a second signal-inversion switching circuit which receives the output of the first signal-inversion switching circuit passing through the signal processing circuit as a second input signal, followed by outputting the second input signal after logic inversion thereof in response to the second state of the switching signal and outputting the second input signal without logic inversion in response to the first state of the switching signal.

Integrated circuit free from accumulation of duty ratio errors

A semiconductor device that operates with reduced power consumption having a clock transfer blocking circuit and an external data transfer blocking circuit that blocks a clock signal and a data signal from being transferred to a data output circuit when a data signal captured by a data capturing circuit is to be latched by a latch circuit. If however, the data signal captured is necessary for a later stage of the semiconductor device, then an internal data transfer blocking circuit blocks the data signal from being latched in the latch circuit, while the clock transfer blocking circuit and the external data transfer blocking circuit cause the captured clock signal and data signal to be output to the data output circuit.

Semiconductor device and liquid crystal panel display driver

A transfer circuitincludes two sets of an input circuitA and an output circuitB, which allows bidirectional transfer. The input circuitA decomposes external input data signals DIA and DIA to signals on lines Lto Lin synchronism with a clock signal CLK in order to reduce the frequency thereof. The output circuitB composes the decomposed signals in synchronism with the clock signal CLK to regenerate the original signals and output them as external output data signals DOB and DOB. Signals on either the lines Lto Lor Lto Lare selected by a multiplexerto provide to a main body circuit.

Semiconductor device equipped with transfer circuit for cascade connection

A Schmitt trigger circuit has a first transistor for inversion having a base supplied with an input voltage. A level shift diode shifts an emitter voltage of the first transistor from a reference level, and a second transistor for switching has a collector and an emitter respectively coupled to an anode and a cathode of the level shift diode. The emitter of the second transistor is coupled to a first power source voltage. A switching part is coupled between a base of the second transistor and a second power source voltage higher than the first power source voltage, for controlling switching of the second transistor. An output circuit is coupled between the first and second power source voltages and supplied with the input voltage through the first transistor for outputting the output voltage. The switching part is controlled responsive to a voltage from the output circuit so as to close when the logic level of this voltage is the high level, thereby turning the second transistor ON.

Schmitt trigger circuit

A logic circuit which reduces occurrence of breakdown of the pull-down transistor and pull-up transistor in the output stage when a high voltage is applied to the power supply line and ensures high voltage resistance. The logic circuit controls a pull-up transistor provided between a first power supply and an output terminal which turns ON and OFF in accordance with a collector voltage of a phase splitter transistor and controls the pull-down transistor provided between the second power supply and output terminal with an emitter voltage. Breakdown of the pull-down and pull-up transistors can be reduced and a high voltage resistance ensured by providing a protection circuit which discharges the base of the pull-down transistor and turns OFF the pull-down transistor by detecting when a voltage difference between the first power supply and the second power supply exceeds a specified value.

Logic circuit

A gate circuit used for controlling an interface circuit in a microcomputer system, including a first-stage gate circuit, a second-stage gate circuit, and a control device connected between the first-stage gate circuit and the second-stage gate circuit. The first-stage gate circuit outputs an inverted strobe signal to the interface circuit, and the second-stage gate circuit outputs a non-inverted strobe signal to the interface circuit. Although there is a time lag in the changeover timing of these strobe signals, this time lag is reduced by connected the diode between the first-stage gate circuit and the second-stage gate circuit.

Growing community of inventors

Kawasaki, Japan

Masao Kumagai