Fujitsu Corporation

Masao Koyabu

Junichi Inagaki

Masahiro Kuramoto

Jun Tsuiki

Hiroaki Ishihata

A network system broadcast data from one node to a plurality of other nodes, which can decrease the time required for broadcast. A transfer source node divides the transfer data to be broadcasted, and transfers each divided data separately from the network adapters of the transfer source node to the network adapters of the other nodes, and the other nodes transfer the received data to the network adapters of the other nodes other than the transfer source node. Since more nodes (network adapters) can participate in data transfer in the second data transfer, high-speed transfer processing can be implemented, and the transfer processing time for broadcast can be decreased.

Broadcast processing method for network system and network system

A computer system execute summation processing even if the computing sequence is not adhered to in a system for computing a sum of floating point data of a plurality of nodes. Each node sends floating point data to a reduction mechanism, and the reduction mechanism computes the sums only for a group of which exponent sections have a highest value and a group of which exponent sections have a second highest value, and adds the sum of the group of which the exponent sections have a highest value and the sum of the group of which the exponent sections have a second highest value. By this, the consistency of the computation result can be guaranteed even if the sum is computed regardless the computing sequence of the values.

Processing method and computer system for summation of floating point data

A parallel computer operates to reduce data held by a plurality of nodes. Each node constituting a parallel computer transfers the data divided into n to other nodes, and each node summarizes the respective 1/n data and operates, then a plurality of nodes transfer the respective operation result to a summarizing node. Since all the nodes execute operation for divided data respectively, reduction processing time can be decreased. And more nodes (network adapters) can participate in data transfer through the first and second data transfers, high-speed transfer processing can therefore be implemented, and transfer time can be decreased.

Reduction processing method for parallel computer, and parallel computer

The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead. The asynchronous transmission device that receives at least one notification signal in accordance with a reception clock, the notification signal being transmitted in accordance with a transmission clock, includes a trigger signal transmission unit that outputs a trigger signal which is based on the symbol period of the notification signal, a notification signal transmission unit that outputs a notification signal which has its timing staggered by a predetermined time period with respect to the timing of the trigger signal output from the trigger signal transmission unit, a trigger signal synchronization unit that synchronizes the trigger signal, and outputs a sampling timing signal which indicates the sampling timing of the notification signal, and a notification signal retention unit that retains the notification signal in accordance with the sampling timing.

Asynchronous transmission device, asynchronous transmission method

A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written to the storage unit with an odd number of bits, generates a check code based on the first and second codes and stores the check code in the storage unit in correspondence with the data written to the storage unit, and conducts an error check based on data read from the storage unit, a check code corresponding to the data read, and a read address, thus detecting a multi-bit address error.

Storage control circuit, and method for address error check in the storage control circuit

The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.

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Kawasaki, Japan

Masao Koyabu