Nec Corporation

Nlt Technologies, Ltd.

Nec Lcd Technologies, Ltd.

Masao Iriguchi

Hiroshi Tsuchi

Naoyasu Ikeda

Shin-ichi Uehara

Nobuaki Takanashi

In an image display device where a lenticular lens, a display panel, and a light source are provided in order from a viewer side, when cylindrical lenses of the lenticular lens are arrayed in a horizontal direction, in first-viewpoint pixels and second-viewpoint pixels of the display panel, openings whose sides which intersect with straight lines in the horizontal direction are not parallel to a vertical direction are formed. And, a shape of the openings of a pair of pixels mutually adjacent in the vertical direction is made line-symmetric with respect to edges of the pixels extending in the horizontal direction as an axis.

Image display device with pixel sections arrayed in a matrix

In a liquid crystal display apparatus, one display pixel has a total of six sub pixels, namely, a red sub pixel for a left eye, a green sub pixel for the left eye, a blue sub pixel for the left eye, a red sub pixel for a right eye, a green sub pixel for the right eye, and a blue sub pixel for the right eye. Those sub pixels are arranged in a square area, two in a horizontal direction along which gate lines extend, three in a vertical direction along which data lines extend. The polarity of the data lines with respect to a potential of a common electrode is inverted every time three gate lines are scanned and every frame.

Liquid crystal display apparatus, portable device, and drive method for liquid crystal display apparatus

Image display device, portable terminal, display panel, and lens

Disclosed is a display device including display unit, a column driver, a delay control circuit, an output switch control circuit, and a display controller. The display unit includes a plurality of pixel electrodes arranged at intersections between a plurality of data lines and a plurality of scan lines in a matrix form and TFTs. One of a drain and a source of each of the TFTs is connected to a corresponding one of the pixel electrodes. The other one of the drain and the source of each of the TFTs is connected to a corresponding one of the data lines, and a gate of each of the TFTs is connected to a corresponding one of the scan lines. The scan driver supplies a scan signal to each of the scan line in a preset scan cycle. The column driver includes D/A converter circuits for converting video data to gray scale signals, a plurality of buffer amplifiers for sequentially amplifying and outputting the gray scale signals in a preset output cycle, and an output switch circuit including a plurality of switches connected to output terminals of the buffer amplifiers and the data lines, respectively. The delay control circuit controls the scan driver so that the preset scan cycle is delayed from the preset output cycle just by a preset delay time. The output switch control circuit controls the output switch circuit to be kept off during the preset delay time. The display controller controls the video data, scan driver, column driver, delay control circuit, and output switch control circuit, respectively.

Active matrix type display device and driving method thereof

Disclosed is a differential amplifier of a multi-level output type comprising a load circuit including a diode-connected first transistor with a source thereof connected to a power supply and a second transistor with a source thereof connected to the power supply and connected to a gate of the first transistor through a capacitor, a differential pair including a third transistor and a fourth transistor with sources thereof connected in common and drains thereof connected to drains of the first and second transistors, respectively, a current source for supplying a current to the differential pair, a first switch connected between a gate of the second transistor and a drain of the fourth transistor, an amplifier with an input thereof connected to a drain of the second transistor and an output thereof connected to an output terminal, a second switch connected between a gate of the fourth transistor and a first input terminal, a third switch connected between the gate of the fourth transistor and a third input terminal, a fourth switch connected between a gate of the third transistor and a second input terminal, and a fifth switch connected between the gate of the third transistor and the output terminal. Switching control between a first state where the first, second and fourth switches are turned on and the third and fifth switches are turned off and a second state where the first and second fourth switches are turned off and the third and fifth switches are turned on is performed.

Differential amplifier, digital-to-analog converter, and display device

A differential amplifier comprises first, second, and third input terminals (and), output terminal (), first and second differential pairs (and) (and) driven by a corresponding current source and having output pairs commonly connected to load circuits (and), and an amplifier stage () having input end connected to at least one of the common connection points of the load circuits and output pairs of the first and second differential pairs and output end connected to output terminal. Input pair of second differential pair receives a signal from third input terminal and a feedback signal from output terminal. First and second switches (SWand SW) are provided between the input pair of the first differential pair and the first and second input terminals (and), and first and second capacitors (Cand C) connected between each connection point of the input pair of the first differential pair and the first and second switches (SWand SW) and a reference voltage terminal are provided. The first, second and third input terminals (and) may be combined into one terminal to which voltages are serially supplied. It avoids the influence of power supply/signal noise and switch noise, and provides operational output from a plurality of input reference voltages.

Differential amplifier and digital-to-analog converter

An offset cancellation amplifier where during a first period of a data output period, an output voltage and a reference voltage are supplied to the gates of a first differential pair, and the output voltage is accumulated in first and second capacitors while an input voltage is supplied in common to the gates of a second differential pair. During a second period, the output voltage is accumulated in the first capacitor, while the reference voltage is accumulated in the second capacitor. During a third period, the gates of the first differential pair cease to be supplied with the output voltage and with the reference voltage, respectively, and are supplied with the voltages accumulated in the first and second capacitors, respectively. The gates of the second differential pair are supplied with the output voltage and with the input voltage, respectively.

Offset cancellation amplifier, display employing the offset cancellation amplifier and method for controlling the offset cancellation amplifier

Disclosed is a multi-level output differential amplifier which includes a first differential pair; a second differential pair; a load circuit commonly connected to output pairs of the first and second differential pairs; first and second current sources for supplying current to the first and second differential pairs, respectively; an amplifier stage for receiving a common output signal of the first and second differential pairs and driving an output terminal by a charging or discharging operation; and a control circuit for controlling changeover of signal inputs to the first and second differential pairs. The data output period includes first and second time periods. In the first time period, a voltage at the output terminal and a reference voltage are applied to first and second differential inputs of the first differential pair; the output-terminal voltage and the reference voltage are stored in first and second capacitors, respectively, connected to the first and second differential inputs of the first differential pair; and first and second voltages are applied to first and second differential inputs of the second differential pair. In the second time period, the first and second differential inputs of the first differential pair are cut off from supply of the output-terminal voltage and supply of the reference voltage and are supplied with the voltages stored in the first and second capacitors, and the output-terminal voltage and a third voltage are applied to the first and second differential inputs of the second differential pair.

Differential amplifier, digital-to-analog converter and display device

Disclosed are a multi-level differential amplifier that includes first to third input terminals; an output terminal; first to third differential pairs; a current source circuit for supplying currents to the respective first to mth differential pairs; a load circuit connected to first and second nodes to which first and second outputs of each of output pairs of the first to third differential pairs are connected in common; an amplifier stage receiving a signal from at least one node of the first and second nodes as an input and having its output connected to the output terminal; and a capacitance element. A data output period includes first and second periods. In the first period, responsive to a control signal, a first input of each input pair of the first to third differential pairs is made a non-inverting input, the second input is made an inverting input, the first inputs are connected to the respective first to third input terminals, and the second inputs of the first to third differential pairs are connected in common with one end of the capacitance element and with the output terminal. In the second period, responsive to a control signal, the first input of each input pair of the first to third differential pairs is made an inverting input and the second input is made a non-inverting input, the first inputs of each of the input pairs are connected in common with the output terminal, and the second inputs are connected in common with the one end of the capacitance element.

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Tokyo, Japan

Masao Iriguchi