Hitachi, Ltd.

Other

Fujitsu Corporation

Masao Inoue

Akira Yamagiwa

Kenji Kashiwagi

Hideki Osaka

Ryoichi Kurihara

Katsuhiro Okumoto

Hisao Honma

Toshihiko Ogura

Koji Matsuda

Kenichi Kurosawa

Toshitsugu Takekuma

Yoshihiro Miyazaki

Shinichiro Yamaguchi

Soichi Takaya

Hiromi Kato

Sako Ishikawa

Masato Honda

Masaki Iwamoto

Toshihiko Fushimi

Kouichi Tsuzuki

Teruyuki Suzuki

The present invention provides a technique for, in the case in which a failure has occurred in a shared memory, controlling a period of a pseudo through operation to reduce a period in which performance of a disk array device falls. Control information is divided into management information, which is required to be duplexed, and directory information, which is only required to simplexed, and the management information and the directory information are stored in separate shared memories. In the case in which a failure has occurred in the shared memory of an expanded memory unit (Option) storing the directory information, the directory information is reestablished in the shared memory of a basic memory unit (Basic). The pseudo through operation is cancelled at the point when the directory information is reestablished. After a package of the expanded memory unit is replaced with a normal product, the directory information is reestablished again. Management information managed in the other cluster is copied to the shared memory of the basis memory unit to complete maintenance and recovery work.

Disk array device and maintenance method for disk array device

An interactive data analysis support apparatus for supporting the analysis of data comprises: a cross tabulation display device for displaying according to specified summing up conditions a cross tabulation in which data to be analyzed is cross summed up, a cell specifying device for specifying at least one cell among a number of cells constituting the cross tabulation, and a graph display device for displaying the data to be analyzed as a graph within the range of the cell specified by the cell specifying device.

Interactive data analysis support apparatus and media on which is recorded an interactive data analysis support program

The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.

Uninterruptible clock supply apparatus for fault tolerant computer system

A data bus circuit includes a plurality of data buses, a plurality of data processing units connected to each of the data buses for performing transmission and reception of data in response to a transmission control signal, at least a termination resistor connected to termination of the plurality of data buses, the termination resistor including a first resistance circuit for suppressing reflection of signals on the plurality of data buses upon transmission and reception of data of the plurality of data processing units and a second resistance circuit having a resistance value larger than that of the first resistance circuit, an output control circuit for producing the transmission control signal as to whether the plurality of data processing units perform transmission and reception of data or not, and a changing-over circuit for changing over to connect the first resistance circuit to the data buses through which transmission and reception of data is performed when at least one of the plurality of data processing units performs transmission and reception of data in response to the transmission control signal and to connect the second resistance circuit to the data buses through which transmission and reception of data is not performed when any of the plurality of data processing units does not perform transmission and reception of data, whereby a current flowing in the termination resistor can be reduced when data is not transmitted on the data bus and the low power consumption of the data bus circuit can be attained.

Data bus circuit and method of changing over termination resistor of the

It is an object of the present invention to provide an active-line inserted/withdrawn functional circuit board, a data transfer system and a computer system which systems allow the functional circuit board to be inserted and withdrawn with signal lines remaining in an active state while achieving a high speed data-transfer of a bus, and the reliability to be enhanced by eliminating malfunctions which occur particularly during the insertion of a functional circuit board. The data transfer system or the computer system comprising: a functional circuit board having a functional circuit, a pre-charge resistor and a switching element connected in parallel to an input/output signal path of the functional circuit and a switching control means for controlling the conduction of the switching element through synchronization with a delayed clock signal resulting from delaying a bus clock signal for use in data transfers through the bus by a time shorter than a bus-clock cycle time of the bus clock signal; and a connector provided on an input/output end of the parallel connection of the pre-charge resistor and the switching element, whereby the functional circuit board can be inserted and withdrawn to and from the bus.

Data transfer system, computer system and active-line inserted/withdrawn

A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself. Each of the intra-block transmission line is provided with a resistance element having a resistance equal to or close to a value derived by subtracting a half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

Fast transmission line implemented with receiver, driver, terminator and

A bus transceiver in a first signal processing circuit is connected to one end of a first bus connecting line for transferring a data pulse signal. A bus transceiver in a second signal processing circuit is connected to one end of a second bus connecting line for transferring a data pulse signal. Connected to the other end of the first bus connecting line is a first termination resistor. Connected to the other end of the second bus connecting line is a second termination resistor. In a portion of a predetermined length (parallel coupling portion) in the first and second bus connecting lines, the interval between the first and second bus connecting lines is held substantially constant so as to produce capacitive and inductive coupling between both the bus connecting lines. Each of the first and second bus transceivers includes a bus driver and a bus receiver. The bus receiver in the first bus transceiver generates a pulse signal substantially equal to an output pulse signal which was generated from the bus driver in the second bus transceiver, based on a pulse waveform induced in the parallel coupling portion on the first bus connecting line by the output pulse signal from the second bus transceiver.

Fast data transfer bus

Growing community of inventors

Sagamihara, Japan

Masao Inoue