Kabushiki Kaisha Toshiba

Masanori Uchida

Tetsuya Iizuka

Takayasu Sakurai

Kazutaka Nogami

Makoto Takahashi

Fumitoshi Hatori

Toshinari Takayanagi

A field programmable gate array comprises: a first wiring group composed of a plurality of first wirings (C1, C2, C3, . . . ); a second wiring group composed of a plurality of second wirings (R1, R2, R3, . . . ); a plurality of programmable elements (A11, A12, A13, . . . ) arranged into an array pattern at at least one of plural intersections between the first wirings and the second wirings, each of the programmable element being connected to each of the first wirings (C1, C2, C3, . . . ) at one end thereof and to each of the second wirings (R1, R2, R3, . . . ) at the other end thereof and being programmed by a programming voltage applied between the first wiring and second wiring to switch connection between the first and second wirings to disconnection between the two wirings or vice versa; and voltage supplying sections (CD1, RD1) for applying a programming voltage between the first and second wirings (C1, C2, C3, . . . ; R1, R2, R3, . . . ) between which the programmable element to be programmed is connected and an intermediate voltage between the first and second wirings between which the programmable element not to be programmed is connected, the intermediate voltage being lower than the programming voltage to such an extent as not to affect state of the programmable elements (A11, A12, A13, . . . ).

Field programmable gate array

The associative memory capable of improving the efficiency in replacing an entry and testability of compare operation. The associative memory includes a Content Addressable Memory (CAM) cell array for executing a compare operation; a Random Access Memory (RAM) cell array for operating responsive to a result of the CAM cell array; and a HIT entry number detection circuit for receiving a result of the compare operation in the CAM cell array and outputting a HIT entry number.

Associative memory system with hit entry detection circuit

According to this invention, a bit data comparing section has a plurality of groups each having a plurality of bit comparators. Each of the plurality of bit comparators compares one bit of address data input to the bit comparator with bit data stored in the bit comparator in advance and outputs a comparison result. Output data from a plurality of bit comparators belonging to one group are unified by one subsense line belonging to the group and input to a control terminal of a switching element. The switching element performs a switching operation in accordance with the input data. A main sense line is connected to the switching element, and a load circuit is connected between the main sense line and a power supply terminal.

Data comparator

An amplifier circuit includes two inverter circuits. Each inverter circuit provides an output signal in response to a respective input signal. The inverter circuits are supplied with a power source voltage through a MOS transistor circuit. The MOS transistor circuit includes two MOS transistors each having gate electrodes supplied with the output of the inverter circuits.

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Yokohama, Japan

Masanori Uchida