Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Masanori Tsutsumi

Junichi Yano

Hiroyuki Tsujikawa

Kenji Shimazaki

Fumihiro Kimura

Shouzou Hirano

Hisato Yoshida

Kaori Matsui

Ritsuko Kurazono

Masayuki Matsuda

In a semiconductor integrated circuit device, from a first power source strap supplying a potential to a first standard cell receiving a supply of the potential, the potential is supplied via a first cell power source line having a constant width. The width of the first cell power source line is determined in accordance with power consumed by the first standard cell and with the number of standard cells that can be placed between the first power source strap and a third power source strap.

Semiconductor integrated circuit device and power source wiring method therefor

A reduction of a current capability of a MOS transistor (P) is compensated by dynamically changing a substrate bias of the MOS transistor (P) in response to a fluctuation of the power supply, and thus an operating speed is stabilized automatically. An NMOS transistor (N) generates a current (I) that changes in response to an extent of fluctuation of the power supply voltage, and then the current (I) is converted into a voltage via a resistor (R) to apply a forward bias to a substrate (back gate) of the MOS transistor (P). When the current capability of the MOS transistor (P) is reduced owing to a reduction of the power supply voltage, an adjustment is carried out automatically to lower a threshold voltage of the MOS transistor and thus the operating speed can be compensated.

MOS transistor circuit

VSSis provided to a gate portionand VDDis provided to a source portionand a drain portionof a MOS transistor which constitutes a decoupling capacitor, and a potential NWVDDdifferent from that provided to the source portionand the drain portionis provided to a substrate portion. If NWVDDis set higher than VDD, a depletion layeris spread, so that a leakage current can be reduced instead of reducing a capacitance of the decoupling capacitor. In addition, if NWVDDis set lower than VDDso as not to cause latchup, the depletion layeris reduced, so that the capacitance of the decoupling capacitor can be increased. By changing the potential NWVDDprovided to the substrate portion, a capacitance value and a leakage current value of the decoupling capacitor can be controlled. Thereby making it possible to achieve a decoupling capacitor capable of controlling the capacitance value and the leakage current value and also having excellent response characteristics.

Decoupling capacitors and semiconductor integrated circuit

By forming adjacent wiringadjacent to signal wiringand using a control circuitcomprising a 2-input NANDcircuit or the like to input a signal Scorresponding to a signal Sin the signal wiringto the adjacent wiringit is made possible to change the delay of the signal Sin the signal wiringin several picoseconds, by using crosstalk with the signal Sin the signal wiringThe inventive delay control circuit device can be provided by simply adding adjacent wiringand a control circuitto signal wiring. This implements a delay control circuit device for semiconductor integrated circuits that is capable of controlling a signal delay in several picoseconds without increasing the circuit scale.

Delay control circuit device, and a semiconductor integrated circuit device and a delay control method using said delay control circuit device

A standard cell for a plurality of power supplies comprises a first power line and a second power line electrically isolated from the first power line. An N well is arranged in spaced relation with the whole peripheral boundaries of the standard cell. In the case where the standard cells are arranged adjacently to each other in the direction along the power lines or in the direction orthogonal thereto, the N well in the standard cell for a plurality of power supplies is isolated from the N wells of the adjacent standard cells in the direction along the power lines or in the direction orthogonal thereto, as the case may be.

Standard cell for plural power supplies and related technologies

An electromagnetic disturbance analysis method for analyzing an external noise to a semiconductor integrated circuit includes an impedance extraction step of extracting impedance information on the power wiring in the target semiconductor integrated circuit or the power wiring in the semiconductor integrated circuit and the external power wiring of the semiconductor integrated circuit, an equivalent circuit creating step of creating an equivalent circuit from the impedance information, and an analysis step of supplying a noise waveform externally and analyzing the influence of the noise on the semiconductor integrated circuit.

Growing community of inventors

Kyoto, Japan

Masanori Tsutsumi