Kabushiki Kaisha Toshiba

Kyushu Institute of Technology

Masanori Tsukuda

Ichiro Omura

Takashi Shinohe

Masakazu Yamaguchi

Masahiro Tanaka

Yamato Miki

A method for fabricating a high-voltage insulated gate type bipolar semiconductor device by comparing to a reference structure of the same includes determining a width S of a mesa region in which the gate insulating film and the MOS transistor are formed, and a trench depth D, based on a scaling ratio K, in comparison with a second width and a second trench depth of the reference structure, and setting a cell width 2W of the high-voltage insulated gate type bipolar semiconductor device to be equal in length to a second length of the reference structure, the scaling ratio K being defined as K=Y/X, where X indicates a size of a target portion to be miniaturized in the high-voltage insulated gate type bipolar semiconductor device, and Y indicates a size of a target portion to be miniaturized in the reference structure.

Method for fabricating high-voltage insulated gate type bipolar semiconductor device

A semiconductor device includes: a first semiconductor layer; a first electrode provided on a first surface side of the first semiconductor layer; a first insulating layer; and a second semiconductor layer. The first insulating layer is provided between the first semiconductor layer and the first electrode and configured to constrict current flowing between the first semiconductor layer and the first electrode. The second semiconductor layer has a first conductivity type and is provided at least on a path of the current constricted by the first insulating layer. The second semiconductor layer is in contact with the first electrode. The second semiconductor layer contains first impurities at a concentration higher than a concentration of impurities contained in the first semiconductor layer.

Semiconductor device

In a vertical semiconductor device including a first base layer of a first conductivity type, second base layers of a second conductivity type, emitter layer of the first conductive type and gate electrodes which are formed at one main surface of the first base layer and including a buffer layer of the first conductivity type, a collector layer of the second conductivity type and a collector electrode which are formed at the other main surface of the first base layer, an electric field relaxing structure selectively formed outside from the second base layers and the collector layer is formed expect the region below the electric field relaxing structure.

Vertical semiconductor device

A semiconductor device includes a semiconductor substrate; a first base region of a first conductivity type provided in the semiconductor substrate; a buffer region of the first conductivity type provided on a lower surface of the first base region and having an impurity concentration higher than an impurity concentration of the first base region; an emitter region of a second conductivity type provided on a lower surface of the buffer region; a second base region of the second conductivity type selectively provided on an upper surface of the first base region; a diffusion region of the first conductivity type selectively provided on an upper surface of the second base region; a control electrode; a first main electrode; and a second main electrode. A junction interface between the buffer region and the first base region has a concave portion and a convex portion.

A semiconductor power device includes a high-resistance semiconductor substrate of the first conductivity type having first and second major surfaces and a recess in either one of the first and second major surfaces, and a semiconductor power element with a field relaxation structure, at least part of which is formed in a region of the semiconductor substrate where the recess is formed.

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Kawasaki, Japan

Masanori Tsukuda