Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Cable, Inc.

Masanori Segawa

Hiroyoshi Kokaku

Masatsugu Ogata

Asao Nishimura

Kunihiro Tsubosaki

Makoto Kitano

Hiroshi Hozoji

Hiroshi Kikuchi

Kunihiko Nishi

Takashi Yokoyama

Gen Murakami

Akio Hasebe

Akihiro Yaguchi

Takashi Yamazaki

Kazuyoshi Oshima

Masahiro Ichitani

Aizo Kaneda

Shozo Nakamura

Junichi Saeki

Isamu Yoshida

Sueo Kawai

Noriyuki Kinjo

Syuuji Eguchi

Ichiro Anjoh

Ichiro Anjo

Tetsuro Matsumoto

Akira Nagai

Shuji Eguchi

Tetsurou Matsumoto

Masahiko Ogino

Toshiaki Ishii

Chuichi Miyazaki

Mamoru Mita

Norio Okabe

Nobutake Tsuyuno

Rie Hattori

Takumi Ueno

Makoto Morishima

Toshiak Ishii

Akio Takahashi

Haruo Akahoshi

Naotaka Tanaka

Takao Miwa

Ichirou Anjou

Ryo Moteki

Yasuhide Sugawara

Satoshi Nakamura

Hidetoshi Abe

Akio Nishikawa

Fumio Sato

Osamu Horie

Ogino Masahiko

Ryou Moteki

A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200&#x2013;250&#xb0; C.).

Circuit tape having adhesive film semiconductor device and a method for manufacturing the same

In a semiconductor device having a three-layered buffer layer comprising core layerhaving interconnected foams such as a three-dimensional reticular structure and adhesive layersprovided on both sides of the core layer as a stress buffer layer between semiconductor chipand wiringto lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of the core layerto total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

Wiring tape for semiconductor device including a buffer layer having interconnected foams

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the 'Lead-On-Chip' or 'Chip-On-Lead' structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Semiconductor device

A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250&deg; C.).

Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the &ldquo;Lead-On-Chip&rdquo; or &ldquo;Chip-On-Lead&rdquo; structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

In a semiconductor device having a three-layered buffer layer comprising core layer having interconnected foams such as a three-dimensional reticular structure and adhesive layers provided on both sides of the core layer as a stress buffer layer between semiconductor chip and wiring to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.

Semiconductor device having a porous buffer layer for semiconductor device

A method of forming a semiconductor device having a multi-layered wiring structure that includes a conductor layer to be electrically connected to a packaging substrate, with the multi-layered wiring structure being provided on a circuit formation surface of a semiconductor chip. Ball-like terminals are formed, disposed in a grid array on the surface of the multi-layered wiring structure on the packaging substrate side. The multi-layered wiring structure is formed to include a buffer layer for relieving a thermal stress provided between the semiconductor chip and the packaging substrate, due to the packaging procedure. In the semiconductor device formed, the wiring distance is shorter than that of a conventional semiconductor device, so that an inductance component becomes smaller, to thereby increase signal speed. The distance between a ground layer and a power supply layer is shortened, to reduce noise produced upon operation, and also a thermal stress upon packaging is relieved by the buffer layer of the multi-layered wiring structure, resulting in improved connection reliability, and the number of terminals per unit can be increased, because of elimination of wire bonding. The buffer layer can be made of an elastomer, and can have a modulus of elasticity of 10 kg/mm or less.

Method of making a semiconductor device having a stress relieving mechanism

Semiconductor device including a resin sealing member which exposes the

A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250.degree. C.).

Circuit tape having adhesive film, semiconductor device, and a method

A laminate capable of mounting semiconductor elements thereon; comprising an insulating layer which is constituted by a resin portion of sea-island structure and a woven reinforcement. The resin portion of sea-island structure is, for example, such that a resin as islands are dispersed in a resin as a matrix. Thus, the insulating layer exhibits a coefficient of thermal expansion of 3.0.about.10 (ppm/K) in a planar direction thereof and a glass transition temperature of 150.about.300 (.degree.C.). Owing to these physical properties, thermal stresses which the laminate undergoes in packaging the semiconductor elements thereon can be reduced, so that the connections of the laminate with the semiconductor elements can be made highly reliable.

Laminate and multilayer printed circuit board

Growing community of inventors

Hitachi, Japan

Masanori Segawa