Sony Corporation

Masanori Noda

Toshinobu Sugiyama

Kenshiro Arase

Ihachi Naiki

Akihiro Nakamura

Tooru Adachi

A semiconductor nonvolatile memory device wherein memory transistors in which data is electrically programmed in units of pages by performing the data programming together for selected memory transistors of a sector selected in response to page program data in units of sectors are arranged in the form of a matrix, provided with a means for continuously inputting the page program data of a plurality of page areas in synchronization with a constant clock pulse and continuously performing the page programming according to the plurality of page program data.

Nonvolatile flash memory with fast data programming operation

A nonvolatile semiconductor memory device capable of being changed in method of use according to its application and in addition having a high reliability and an IC memory card using the same. An IC memory card is provided with multi-level type flash memory chips and a controller as principal constituent elements and constituted so as to allow free selection of plurality of operation modes according to the application, that is, use where a storage capacity is large, but there is a reduction in the write/erase speed or the guaranteed number of the repeated rewrites or use where the storage capacity is small, but there is no reduction in the write/erase speed or the guaranteed number of the repeated rewrites.

Nonvolatile semiconductor memory device and IC memory card using same

A semiconductor nonvolatile memory wherein memory cells in which data is electrically processed are arranged in the form of a matrix, provided with an error correcting circuit for correcting error bits when there are less than a predetermined number of error bits in a plurality of bits of data; a circuit for processing data in units of the plurality of bits of data in the memory cells of the plurality of units and for counting the number of the unprocessed memory cells after data is processed; and a circuit for ending the processing of the data while leaving the unprocessed memory cells when the number of the unprocessed memory cells is less than the predetermined number of error bits and making the error correcting means save the error bits.

Nonvolatile semiconductor memory with fast data programming and erasing

According to this invention, after a semiconductor nitride film is formed on the entire surface of a semiconductor memory device, the semiconductor nitride film on a memory cell portion is removed. After a semiconductor oxide-based film is formed as an interlayer insulator on the entire surface of the semiconductor memory device, the semiconductor oxide-based film on a peripheral circuit portion is removed using the semiconductor nitride film as a stopper. For this reason, a shallow contact hole is formed in the peripheral circuit portion, and highly reliable wiring can be obtained. In addition, since hydrogen can be supplied to a surface of a semiconductor substrate in the memory cell portion by hydrogen annealing, an interface state on the surface can be eliminated, and the data retention characteristics of the memory cells can be improved.

Method of forming a semiconductor memory device having silicon nitride

Semiconductor memory device having silicon nitride overlying only

A method of manufacturing a ROM which has a memory cell array with a plurality of MIS transistors which are serially connected. An impurity of the same conductivity type as the semiconductor substrate is introduced by ion implantation after forming a field oxide and a gate electrode so as to compensate for an impurity of the opposite conductivity type, which is simultaneously ion implanted beneath the field oxide following ion implantation for programing so as to penetrate the gate electrode and a gate oxide. Punch through between adjacent cells is suppressed by the impurity of the same conductivity type.

Method for manufacturing a semiconductor integrated circuit device

A non-volatile semiconductor memory is provided having a memory cell formed in a semiconductor substrate and arranged in rows and columns to form an X-character shape array. Each cell includes a control electrode and a first region and a second region having a conductivity-type different from that of the substrate. Alternate first and second column lines are provided wherein the first region and the second region of each cell in each column are coupled to the first column line and the second column line, respectively. The first column lines selectively function as ground lines for inputting data during a data writing mode. The first column lines function as bit lines, and the second column lines function as ground lines for outputting data during a data reading mode.

Non-volatile semiconductor memory having commonly used source or drain

According to this invention, a semiconductor non-volatile memory is formed as follows. In an EPROM memory array consisting of MIS transistors arranged in a matrix form, a first bit line consisting of polysilicon is connected to a drain region through a first contact formed in the drain region, a second bit line formed on the first bit line through an interlayer insulator by a metal film is connected to the first bit line by a second contact, and the second contact is formed on each source line of the memory array.

Semiconductor memory device

In a semiconductor memory having word lines and power source lines such as bit lines, two word lines extending on both sides of each contact hole of one of the power source lines extending adjacent to each other extend between two adjacent contact holes of the other power source line, which are staggered from the contact hole of the one power source line. A peripheral circuit of the semiconductor memory can be simplified although the memory is suitable for high-speed operation and high integration.

Semiconductor memory

A nonvolatile semiconductor memory device having memory cells in which a control gate is stacked on a floating gate through an insulating film. The memory device has redundant memory cells so as to compensate defective memory cells and a transistor to select the redundant memory cells and the redundant memory cells and the transistor to select the redundant memory cells are formed by a nonvolatile memory transistor. The transistor to select the redundant memory cells has a structure in which the upper surface and side walls of the floating gate are covered by a control gate or a structure in which the floating gate and control gate are covered by a light shielding film and an antireflection film formed under the light shielding film. In a nonvolatile semiconductor memory device having memory cells of a structure in which a control gate is stacked on a floating gate through an insulating film, a phosphosilicate glass film is formed on side walls of the floating gate and the control gate and a silicon nitride film and an arseno-silicate glass film or boro-phospho-silicide glass film are sequentially formed so as to cover the control gate.

Growing community of inventors

Kanagawa, Japan

Masanori Noda