Seiko Instruments Inc

Sii Semiconductor Corporation

Masanori Miyagi

Haruo Konishi

Kazuaki Kubo

Yoshikazu Kojima

Yutaka Saitoh

Toru Machida

Tetsuya Kaneko

Toru Shimizu

Fumiyasu Utsunomiya

Jun Osanai

Yukio Suzuki

Naoto Saitoh

Taro Yamasaki

Masanao Hamaguchi

Youichi Endo

Masashi Sakai

Provided is a non-volatile semiconductor storage device which can be downsized with a simple circuit without impairing the function of an error correcting section, and a method of testing the non-volatile semiconductor storage device. An error correction circuit is configured to perform error detection and correction of merely the same number of bits as data bits, and a circuit for performing error detection and correction of check bits is omitted to downsize the circuit. A multiplexer for, in a testing state, replacing a part of the data bits read out from a storage element array with the check bits, and inputting the check bits to the error correction circuit is provided. Thus, error detection and correction of the check bits are performed to enable shipment inspection concerning the check bits as well.

Non-volatile semiconductor storage device and method of testing the same

Provided is a radio communication apparatus using a battery as a power supply, in which standby electricity is reduced to achieve a reduction in power consumption. The radio communication apparatus includes a time measuring unit () and a plurality of time signal outputting units (to) such that a plurality of circuit blocks are intermittently operated for a minimum period of time, only a necessary circuit block is intermittently operated, or an intermittent operation is performed with a minimum power supplied, at desired independent time intervals or after desired independent elapsed time.

Radio communication apparatus

A semiconductor integrated circuit device has an electrically rewritable non-volatile memory that operates with a first power supply, and a second circuit that operates with a second power supply having a voltage lower than the voltage of the first power supply. The second circuit has a gate oxide film which is thinner than the gate oxide file of the electrically rewritable non-volatile memory. A depletion NMOS transistor has a gate connected to the second power supply, a gate oxide film whose thickness is the same as that of the gate oxide film of the electrically rewritable non-volatile memory, and transmits a signal from an output terminal of the electrically rewritable non-volatile memory to an input terminal of the second circuit.

Semiconductor integrated circuit device

A latch circuit is configured so that even if a power-on-reset circuit is not operated in putting a power supply to work, a depletion type MIS transistor is connected as a pull-down element to an output terminal of an RS latch to thereby reliably activate the RS latch in a reset state, whereby a circuit or a semiconductor integrated circuit device is prevented from being unintendedly operated. Furthermore, channel impurities of the depletion type MIS transistor are introduced into only a part, whereby it is possible to realize a semiconductor integrated circuit device which is excellent in safety and which is readily operated with less current consumption and with low cost.

Latch circuit for holding detection state of a signal

A MOS semiconductor device is manufactured by providing a gate electrode on a semiconductor substrate through a silicon oxide film and disposing a resist mask pattern in contact with the silicon oxide film. The resist mask pattern has a fully opened region and a partially opened region disposed between the fully opened region and the gate electrode. The partially opened region has alternating masked portions and portions exposing the silicon oxide film which partly block and partly permit, respectively, the introduction of impurities therethrough. Impurities are selectively introduced into an impurity introduction region of the semiconductor substrate through the fully opened region and the partially opened region of the resist mask pattern to form areas having high and low impurity densities in the impurity introduction region.

Method of manufacturing semiconductor device

There is provided a voltage detecting circuit in which a consumed electric current is small, accuracy is high, and an erroneous operation seldom occurs. In the voltage detecting circuit constituted by a bias circuit, a current mirror circuit, a load MIS transistor connected to the current mirror circuit in which current drive capability is changed by an output voltage of the bias circuit, and an amplifying inverter circuit, a potential change at an output node of the current mirror circuit at the time of detection and release of a power supply voltage is steeply changed, so that a leak current of the whole circuit can be decreased and a consumed electric current can be reduced. Besides, plural load P type MIS transistors of the bias circuit are prepared, so that a detection voltage and a release voltage can be made to have hysteresis, abnormal oscillation of a detection output VDETX in the vicinity of the detection and release voltage can be prevented, and an erroneous operation of a logic circuit to which the detection output is applied can be prevented.

Voltage detecting circuit

A latch circuit is arranged by means for detecting a signal, a unit for holding a signal detection condition, and a unit for releasing the signal detection condition. When a detection output produced from the detecting unit is entered into the signal detection condition holding unit, the signal detection condition holding unit continuously holds the detection condition until a power supply is interrupted even when the detection output is not entered thereinto. The signal detection condition releasing unit produces a release signal only when the power supply is turned ON. Once the signal detection condition holding unit holds the signal detection condition, the signal detection condition holding unit is reset to an undetection condition only when the power supply is interrupted and then is again turned ON. The latch circuit can firmly reset the stopped system to the initial condition by merely again turning ON the power supply. In addition the stopped system is not unnecessarily reset until the power supply is interrupted. As a consequence, it is possible to obtain the safety operation as well as the firm operation of the circuit and the system.

Latch circuit

A non-volatile memory circuit has FLOTOX type memory elements operable with a low data writing voltage even when a difference between threshold voltages of non-volatile memory elements is small. Each data bit is held by two non-volatile memory elements for storing data having a complementary logic relationship. Potentials at data lines are supplied to inputs of a sense amplifier so that even a small potential difference can be detected. As a result, data stored in a pair of non-volatile FLOTOX type memory elements having shallow data writing depths can be read.

Complementary non-volatile memory circuit

A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a first conductivity type and the first inversion region of the channel has a first impurity concentration determined by the surface concentration of the substrate. The second inversion region of the channel has a second impurity concentration determined by doping an impurity to the region selected by a photolithographic process. The first and second inversion regions may be divided into a plurality of plane shapes and the threshold voltage of the MISFET is set to a desired value in accordance with the plane area ratio of the first and second inversion regions.

Semiconductor device and manufacturing method thereof

Memory circuit

In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. The channel region,having a first impurity concentration determined by a surface concentration of a P-type semiconductor substrate and a channel region,having a second impurity concentration determined by doping an impurity to the region selected by a pattern,of a mask for doping impurity by ion implantation and others are provided in a channel region of an N-type MOSFET on the P-type semiconductor substrate. The channel region,having the first impurity concentration and the channel region,having the second impurity concentration are divided into a plurality of plane shapes. The channel region of the same MOSFET may be structured by the plurality of plane shapes having the plurality of impurity concentrations as described above and a threshold voltage of the MOSFET may be readily set to a desired value in response to a plane area ratio of the area having the first impurity concentration and the area having the second impurity concentration, allowing to realize a high performance semiconductor integrated circuit device at low cost.

An low-power consumption integrated ring oscillator capable of stable operation throughout a wide voltage range without undergoing a large frequency change includes a first constant voltage generating circuit having an enhancement mode P-MOS transistor and a depletion mode N-MOS transistor and a second constant voltage generating circuit having a depletion mode N-MOS transistor and an enhancement mode N-MOS transistor. A first constant voltage generated by the first constant voltage circuit is applied to a gate electrode of a P-MOS transistor of transmission gates connected between respective cascaded inverters of the ring oscillator. A second constant voltage generated by the second constant voltage generating circuit is connected to the gate electrode of an N-MOS transistor of the transmission gates. By this construction, current consumption is reduced and battery lifetime can be increased. The boosting circuit for writing and erasing an EEPROM circuit may be formed with the low power ring oscillator.

Low power oscillation circuit and non-volatile semiconductor memory having ring oscillator

In a non-volatile memory capable of electrically rewriting data, a timer circuit for determining writing time that is operable at any time at a voltage of under 1.0 V. The timing circuit has a regulated voltage circuit for outputting a regulated output voltage no greater than 1.0 V, a constant current circuit for producing a constant current having a value determined by the regulated output voltage, a voltage comparing circuit for comparing an input voltage input to one terminal with a reference voltage input to another terminal, and a capacitive element connected to a constant current output terminal of the constant current circuit. A connecting point of the constant current output terminal of the constant current circuit and the capacitive element is connected as the input voltage to the voltage comparing circuit, so that a desired time period is determined by comparing a voltage to the terminal of the voltage comparing circuit connected to the capacitive element with the reference voltage connected to the other terminal of the comparing circuit.

Writing signal timer output circuit which includes a bistable timer

A semiconductor integrated circuit device comprises at least two MISFETs formed on a semiconductor substrate and connected in series in a diode connection. Each of the MISFETs has a source, a drain, a channel extending between the source and the drain, and a gate disposed over the channel through a gate insulating film. One of the MISFETs has a first threshold voltage, and the other of the MISFETs has a second threshold voltage lower than the first threshold voltage. A portion of the channel of the semiconductor substrate of each of the MISFETs has an impurity concentration equal to or less than 6.times.10.sup.14 atoms/cc.

Growing community of inventors

Chiba, Japan

Masanori Miyagi