Mitsubishi Electric Corporation

Renesas Electronics Corporation

Renesas Technology Corp.

Masanori Kurimoto

Yuki Iwagami

Akira Yoshida

Hiromi Fujita

Yoshitake Nishiuma

Shigeru Kuriyama

Takayuki Yanai

Chie Hiramine

Masahiko Oomura

Masamitsu Uchiyama

Takeshi Shibagaki

The vehicle electronic control apparatus includes two or more FPGAs that each receive information from the sensor, a nonvolatile memory that holds a bit stream for determining a configuration for the FPGA, an MCU that incorporates two or more nonvolatile memories, in each of which a program code for calculating the control command is installed, and an error control module that outputs an error signal to the outside at a time when an abnormality occurs in at least one of the FPGA and the nonvolatile memory incorporated in the MCU; the nonvolatile memory that holds the bit stream and the nonvolatile memory incorporated in the MCU can be accessed from the outside.

Vehicle electronic control apparatus

Provided is a gain control amplification device having a wide range and high accuracy and configured to adapt measurement target current to the input range of an A/D converter. The gain control amplification device includes: a plurality of differential amplifiers having different gains with respect to measurement target current or voltage; a threshold control circuit for comparing output of the differential amplifier with threshold voltage; a switch for selecting output of one of the plurality of differential amplifiers on the basis of output of the threshold control circuit; and an offset control circuit OF and an addition circuit for adding offset voltage to output of one of the differential amplifiers.

Gain control amplification device

Even when parts having individual differences among identical parts or differences in deterioration speed between parts, or a part that does not have a non-volatile memory such as an EEPROM in a chip of the part itself, are mixed, there is no deterioration diagnosis device that can appropriately diagnose a state of deterioration due to temporal change or the like, because of which a mechanism (correction methodology) for evaluating and correcting deterioration in the precision or performance of an electronic part that has low precision or considerable temporal deterioration, and does not have a correction function, is incorporated in a deterioration diagnosis device, and a deterioration state is diagnosed using incorporated deterioration determination means when using a product after shipping.

Deterioration diagnosis device

A driving deviceincludes: a fault detection devicethat determines a fault in an actuator; a serial interfacethat communicates with an MCU; a memory devicethat stores a program received from the MCUand a fault determination result by the fault detection device; a CPUthat causes the fault detection deviceto execute the fault determination according to a fault determination request from the MCU; a timer devicethat measures a limit time over which fault determination is performed and a determination period of fault determination; and a counter devicethat counts the number of repeats of fault determination and the number of fault occurrences in the actuator

Driving device

An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.

Semiconductor device

A logic simulation apparatus is provided with a circuit dividing unit () that selects and defines logic cones each of which carries out a logic operation in synchronization with one clock domain as target portions to be speeded up from logic cones extracted by a logic cone extracting unit (), and that defines logic cones each of which carries out a logic operation based on a plurality of clock domains as nontarget portions not to be speeded up, and a logic compressing unit () that compresses the logic of each of the target portions, and performs a logic simulation on each of the target portions whose logic is compressed and also on performs a logic simulation on each of the nontarget portions.

Logic simulation apparatus for performing logic simulation in high speed

The outputting of an output pulse produced in response to the inputting of a data pulse and a clock pulse to a D type flip-flop circuit is repeatedly simulated in a simulation process to extract a pulse time difference between the data pulse and the clock pulse as a timing verification checking value in a checking value extracting process on condition that the level of the output pulse becomes higher than a reference voltage until a simulation completion time and the pulse time difference is within a prescribed range. After the first simulation, an optimum simulation completion time, at which the levels of the data pulse, the clock pulse and the output pulse are respectively set to a constant high value, is determined to be place the optimum simulation completion time between a simulation start time and the simulation completion time, and the level of the output pulse is checked at the optimum simulation completion time in simulations following the first simulation. Therefore, a pulse time difference sufficiently made small can be rapidly and reliably extracted as a timing verification checking value.

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Tokyo, Japan

Masanori Kurimoto