Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Hitachi, Ltd.

Masanori Kojima

Naotaka Hashimoto

Hiromi Abe

Shinichi Fukada

Hiroshi Momiji

Masayuki Suzuki

Masayuki A Suzuki

Masashi Sahara

Katsuhiro Uchimura

Fumiaki Endo

Hideaki Kanazawa

Masakazu Sugiura

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and' a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt suicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Method of fabricating semiconductor device

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Method for fabricating semiconductor device

In a high-performance semiconductor integrated circuit, the standby current is reduced by preventing current leakage in a semiconductor integrated circuit device, for example, the memory cell of an SRAM. A gate electrode G is formed on semiconductor substrateand n-type semiconductor regions(source/drain regions) are formed in the semiconductor substrate on both sides of this gate electrode. Within the same apparatus and under near-vacuum conditions, a depth of 2.5 nm or less is etched away from the surfaces of the source/drain regions and gate electrode, a film of Co is then formed on the source/drain regions, and thermal processing is applied to form CoSilayer. As a result, current leakage in the memory cell can be prevented and this method can be applied to semiconductor integrated circuit devices that have low current consumption or are battery-driven.

Semiconductor integrated circuit device and the process of the same

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and' a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region ( ), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide , so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

A implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (,), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide,, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

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Fussa, Japan

Masanori Kojima