Other

Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Engineering Corp.

Masanori Isoda

Masanao Yamaoka

Hiroki Fujisawa

Koji Nii

Yasuhisa Shimazaki

Noriaki Maeda

Yoshihiro Shinozaki

Kazuhiko Kajigaya

Takeshi Sakata

Tomonori Sekiguchi

Katsutaka Kimura

Hitoshi Tanaka

Kiyoo Itoh

Yoshinobu Nakagome

Tsugio Takahashi

Chiaki Dono

Seiji Narui

Yasushi Watanabe

Hiroshi Otori

Akira Ohta

Tatsumi Uchigiri

Eiji Kume

Eiji Yamasaki

Minoru Ebihara

Takayuki Kawahara

Hidehiro Fujiwara

Koji Nll

A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state.

Semiconductor device having identification information generating function and identification information generation method for semiconductor device

The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

Semiconductor integrated circuit device

The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other. The outputs of the transistors act so as to cancel out fluctuations in well potential.

Semiconductor integrated circuit

Data breakdown due to fluctuation of an operation power source is suppressed by suppressing a sub-threshold leakage current. A semiconductor integrated circuit includes a pair of power source wires, a plurality of static memory cells, a voltage control circuit for controlling an operation voltage applied from the power source wires to the static memory cells, a monitor circuit for monitoring a voltage of the power source wires and a mode control circuit for controlling a plurality of operation modes. The monitor circuit can detect a change of decrease of a potential difference between the pair of power source wires. The voltage control circuit can execute control in such a manner as to reduce the potential difference of a pair of power source nodes of the static memory cell in response to indication of the low power consumption mode by the mode control circuit and can execute control in such a manner as to increase the potential difference of the pair of power source nodes of the static memory cell in response to detection of the decrease of the potential difference between the pair of power source wires by the monitor circuit.

It is an object of the present invention to allow a voltage generating section which produces a high voltage to efficiently produce a high voltage, and to reduce a layout area of a semiconductor chip. An intermediate voltage charge pump circuit is provided in a voltage producing section of a flash memory. The intermediate voltage charge pump circuit comprises switching elements, a first charge pump circuit comprising capacitors, a second charge pump circuit comprising switching elements, capacitors and an equalizer comprising switching elements. These elements are driven by driving signals. A period during which all of one contacts of parasitic capacities Capacitor are brought into floating state temporarily is formed. After corresponding parasitic capacities are short-circuited by the switching elements, nodes thereof are electrically charged or discharged, and a high voltage is produced while reusing electric charge while using electric charge discharged to a reference potential by next cycle.

Nonvolatile memory and processing system

In a semiconductor integrated circuit including a first storage having memory cells of a first configuration and a second storage having memory cells of a second configuration, according to a first combination (CS, RAS, CAS, and WE&equals;&ldquo;L&rdquo; and A &equals;&ldquo;0&rdquo;) of control signals (CS, RAS, CAS, and WE) input to control terminals and at least a part of signals input to address terminals to which an address signal (A ) for selecting a memory cell in the first storage is input, an access to the first storage is instructed. According to a second combination (CS, RAS, CAS, WE&equals;&ldquo;L&rdquo;, and A &equals;&ldquo;1&rdquo;) of the signals input to the control terminals and at least a part of signals input to the address terminals, an access to the second storage is instructed.

Relief units (UNITb) each having electrically programmable electric fuses for storing information according to the difference in threshold voltage, and an address comparator are disposed in a second area, and relief units (UNITa) each having laser fuses and an address comparator are disposed in a first area. Both areas are adjacent to each other along an address signal wiring for each comparator, and the address signal wiring is laid out linearly. Even if the electric fuses and the laser fuses are caused to coexist for relief address storage, the difference between by-chip occupied areas due to the difference between their configurations can be adjusted based on the size extending in the direction of the address signal wiring, and an increase in the by-chip occupied area can be restrained to the utmost from a layout viewpoint.

Semiconductor memory including a circuit for selecting redundant memory cells

Growing community of inventors

Sayama, Japan

Masanori Isoda