Sharp Kabushiki Kaisha Corporation

Masanori Inamori

Hiroki Doi

Toshihide Miyake

Toshiya Fujiyama

Tetsuya Akamatsu

Syouji Sakurai

A semiconductor integrated circuit is so structured that a first insulating layer is formed on a surface of a semiconductor chip and a second insulating layer covers an entire region of the surface of the semiconductor chip. Via apertures made to the second insulating layer, an electrical connection configuration is formed from above the second insulating layer by using gold wires. Then, an electronic component is mounted on the second insulating layer. By arranging as such, the electronic component is mounted on the semiconductor chip in advance. Therefore, it is possible to further reduce mounting space on a printed-wiring board and also possible to make is easy to attain one-packaged IC.

Manufacturing method for semiconductor integrated circuit, semiconductor integrated circuit, and semiconductor integrated circuit apparatus

A power-on reset circuit comprises a power supply voltage detection circuit that detects a rise of a power supply voltage and that changes a logic level of a first internal node; a capacitor charge/discharge circuit that charges and discharges a capacitor according to the first internal node level and that in an event that the power supply voltage is reduced, discharges the capacitor to follow the event; and a reset pulse generation circuit that before the power supply voltage rises higher than the predetermined voltage, outputs a first output voltage to an output node and that after the power supply voltage has risen higher than the predetermined voltage, outputs a second output voltage to the output node upon detecting that a charge level of the capacitor has become higher than a charge level detection voltage.

Power-on reset circuit

In a negative voltage output charge pump circuit, first a capacitor C is charged with a positive voltage Vin relative to a reference voltage, and then the high-potential terminal A of the capacitor C is made to conduct to the reference voltage and simultaneously the low-potential terminal B of the capacitor C is made to conduct to an output terminal OUT so that the voltage with which the capacitor C is charged is output as a negative voltage &minus;Vin. Here, at least one of the switching device DP that is kept on while the capacitor C is being charged so as to apply the reference voltage to the point B and the switching device DP that is kept on while the negative voltage is being output so as to make the point B conduct to the output terminal OUT is a depletion-type transistor. This configuration makes it possible to realize a negative voltage output charge pump circuit that is free from malfunctioning caused by a parasitic device, that operates with low loss, and that can be produced at low costs.

Negative voltage output charge pump circuit

A Hall device biasing circuit includes a plurality of terminals for applying a bias voltage to a plurality of Hall devices connected in series, respectively. A magnetism detection circuit includes a plurality of Hall devices connected in series; and a Hall device biasing circuit including at least a plurality of terminals corresponding to the plurality of Hall devices for supplying a constant bias voltage to each of the plurality of Hall devices respectively from the plurality of terminals.

Hall device biasing circuit and magnetism detection circuit including the same

A phase control circuit which can stabilize voltage control when used in a switching regulator, and a switching regulator using such a phase control circuit are provided. A switching circuit for generating a first and a second output signals having opposite polarities based on a clock signal, is provided. A PWM latch circuit, reset by a reset signal, for generating a third and a fourth output signals which have phases controlled with respect to the first and the second output signals respectively by a set signal produced based on a control signal and come to have opposite polarities, is provided. A delay circuit for delaying the rising of each of the first through the fourth output signals before outputting each of the first through the fourth output signals is provided for each output signal. A delay clock pulse width setting circuit for generating a delay pulse based on low level periods of the delayed first and second output signals is provided so as to reset the PWM latch circuit using the delay pulse as the reset signal.

Phase control circuit and switching regulator

A delay circuit in accordance with the present invention includes: a first I L inverter and a second I L inverter connected in cascade with each other; and a capacitor interposed between a ground and a connecting point of the first and second inverters, wherein: the delay circuit further includes a current adjusting circuit having at least one third I L inverter with a plurality of output terminals at least one of which is connected to an input terminal of the third I L inverter; and the current adjusting circuit is connected to adjust a charge current of the capacitor. The configuration provides a delay circuit of simple circuit structure that accounts for a small area in an integrated circuit and that is capable of introducing any given delay and also provides a ring oscillator incorporating the delay circuit.

Delay circuit and ring oscillator incorporating the same

An IIL reset circuit includes an IIL inverter having input and output terminals, and a capacitor connected to the IIL inverter through the input terminal. When the IIL inverter is supplied with a constant current, it charges the capacitor through the input terminal, and outputs a reset pulse through the output terminal. The reset pulse has a pulse width that is determined based on both a current supplied to the capacitor, and on a capacitance of the capacitor.

IIL reset circuit

The invention presents a differential circuit capable of compensating for an error in differential output caused by voltage drop due to the emitter series resistance of transistors without being affected by the values of differential input currents and the current ratio of the input currents. A differential circuit comprises NPN type first and second transistors QA, QB, first and second resistors RA, RB connected between the collectors of the first and second transistors and a DC source voltage, means for connecting the collector of the first transistor to the base of the second transistor, means for connecting the collector of the second transistor to the base of the first transistor, first and second differential current input terminals TA,TB connected to the emitters of the first and second transistors, NPN type third and fourth transistors having their bases connected to the emitters of the first and second transistors, and emitters commonly connected to a constant current source IO, and first and second output terminals T1, T2 connected respectively to the collectors of the third and fourth transistors.

Self compensating differential circuit

There are provided a first constant-current circuit and a second constant-current circuit, and a first resistor connected in series with the first constant-current circuit generates a band-gap voltage. The first constant-current circuit and the second constant-current circuit constitute a current Miller circuit, and a part of a current that flows through the second resistor connected in series with the second constant-current circuit is outputted as a constant current source. The constant-current power supply IC, which has the above-mentioned arrangement, is designed as follows: the first resistor and the second resistor have a predetermined line-width ratio that is determined in such a manner that if the respective line-widths vary by virtually the same value, a varied amount in the second constant current value that has been caused by a variation in the value of resistivity of the first resistor is cancelled by a varied amount caused by a variation in the value of resistivity of the second resistor. This arrangement is effective in compensating function and makes it possible to minimize the error on the constant current output due to deviations that occur during production.

Constant-current power-supply circuit formed on an IC

A log compressing circuit is arranged so that the clamping level is independent of the amplification factor of a first transistor for amplifying input current. The log compressing circuit includes the first transistor for amplifying input current, a compressing diode for log-compressing the amplified current, a clamp voltage generating diode serving as a source for generating a clamping voltage, and a second transistor for clamping the log-compressed voltage if the voltage goes beyond a predetermined clamp voltage. The second transistor has the same form as the first transistor and provides a collector connected to a cathode of the clamp voltage generating diode. The constant current is supplied to the second transistor from a constant current source.

Log compressing circuit providing capability of keeping clamp level

For use with an automatic focusing device, a semiconductor integrated circuit is provided for measuring distance having a light-detecting element for receiving light from an object, the distance to the subject is to be measured, and outputting a signal according to the distance from the object. The semiconductor integrated circuit is formed in one chip and includes a distance measurement arithmetic unit for forming digital distance measurement data inversely proportional to the distance to the object from the signal from the light-detecting element; a memory unit for writing therein two items of distance measurement data output from the distance measurement arithmetic unit with regard to two known distances in a calibration mode, and a data arithmeteic unit for computing an automatic focusing device control signal from the two items of distances measurement data stored in the memory unit and distance measurement data output from the distance measurement arithmetic unit in a distance measuring mode.

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Tenri, Japan

Masanori Inamori