Hitachi, Ltd.

Trio Kabushiki Kaisha

Hitachi Video Engineering, Incorporated

Hitachi Video Eng. Inc.

Masanori Ienaka

Yasuo Kominami

Kazuo Watanabe

Takeshi Wada

Yukihiko Miyamoto

Tsuneo Yamada

Makoto Homma

Yukio Suzuki

Masahiro Yamamura

Yoshitomo Kuwamoto

Hideaki Watanabe

Hidefumi Kimura

Yoshimi Iso

Junichi Nakagawa

Jun'ichi Nakagawa

Masami Kawamura

This invention relates to a phase coincidence detector for examining whether or not two input digital signals are coincident by utilizing a delay signal and an advance signal of a digital phase comparator which examines the phase difference between the two input digital signals and outputs the delay signal representing the delay of one of the input signals to the other and the advance signal representing the advance of one of the input signals to the other. Particularly, the output signals of the phase comparator, that is, the delay signal and the advance signal, are periodic pulse signals, and residual pulses having a small pulse width occur periodically even at the time of coincidence. The phase coincidence detector of this invention changes the delay and advance signals by a pulse width discrimination circuit for discriminating whether or not the phase difference between the two input signals is below a certain constant value, and samples the changed signals to output the in-phase and out-of-phase state as signals having different levels.

Phase coincidence detector

In an intermittently operative phase-locked loop, in order to prevent the oscillator frequency from significantly changing at the time of turning on of an electric power source, a point in time at which a phase difference between clock signals respectively fed to a reference frequency divider and to a frequency divider for dividing the output frequency of a voltage-controlled oscillator becomes substantially zero is detected, and the two frequency dividers are initialized when the above-mentioned point in time is detected after turning on of the electric power source.

Power saving intermittently operated phase locked loop

Signal transmitting operation is effected in a muting circuit when a first constant current source connected to the emitters of first and second transistors is operative with a second constant current source connected to the emitters of third and fourth transistors being inoperative. The signal transmitting operation is not effected in the opposite case. A bias resistor is interposed between the bases of the first and third transistors. To eliminate the popping noise when the power source is turned on, a switching element is connected parallel to the bias resistor and is kept in the ON state for a predetermined period of time after making of the power source. In an FM radio receiver, the output signal of a detuning detection circuit is applied to the input terminals of first and second mute control circuits, and the muting operation of a pre-amplifier for amplifying a stereo composite signal is controlling by the first mute control circuit while the muting operation of a muting circuit connected to the output of a stereo demodulation circuit is controlled by the second mute control circuit. Discrimination levels of these first and second mute control circuits are set to mutually different levels to eliminate occurrence of the popping noise at the time of changes from tuning to detuning and vice versa.

Muting circuit for an FM radio receiver

An FM detector is constructed of a phase shift network and an analog multiplier. The analog multiplier includes a differential amplifier circuit and a phase detector circuit. The differential amplifier circuit includes differential pair transistors which are driven by FM intermediate frequency signals. One of the differential pair transistors has another transistor connected thereto which is also driven by the FM intermediate frequency signal. A collector signal of either one of the differential pair transistors is applied to the phase detector circuit through the phase shift network, while a collector signal of the other transistor is directly applied to the phase detector circuit. An emitter of the one transistor and an emitter of the other transistor are connected through resistors, whereby the signal-to-noise ratio of the FM detector is improved.

FM Detector using a phase shift network and an analog multiplier

Stereo composite signals and 38 KHz sub-carrier switching signal are fed to a stereo demodulator. The 38 KHz sub-carrier switching signal is generated from the phase-lock loop circuit and is transmitted to the stereo demodulator circuit via a gain-controlled circuit. The output of an FM detector is applied to a high-pass filter which works to take out undesirable high-frequency components that are contained in the FM detection outputs. The level of the high-frequency components is detected by a detector. The output signal of the detector is applied to the gain-controlled circuit to control the gain of the gain-controlled circuit. When the level of undesirable high-frequency components obtained by the high-pass filter increases, the gain of the gain-controlled circuit is decreased, whereby the amplitude level of 38 KHz sub-carrier switching signal transmitted to the stereo demodulator is lowered. Thus, it is possible to suppress the development of beat signals of audible frequencies, due to the interference between undesirable high-frequency components contained in the outputs of the FM detector and harmonic components in the 38 KHz sub-carrier signals.

FM Receiver

An output from an OCL type power output circuit is applied to a loudspeaker load through a switching means such as a relay. A first detector circuit and a second detector circuit detect a first operating status (e.g., output d.c. level) and a second operating status (e.g., output current level of an output transistor) of the OCL type power output circuit, respectively. The detection output signals of the first detector circuit and the second detector circuit are respectively applied to a first detecting transistor and a second detecting transistor. In the normal operation status of the OCL type power output circuit, the first detecting transistor and the second detecting transistor are respectively biased into 'on' states by the first detector circuit and the second detector circuit so as to permit predetermined currents to flow. When the first and second detecting transistors are in their 'on' states they control a driving transistor into an 'on' state. Then, the switching means, such as a relay, is controlled into a closed state. In the abnormal operation status of the OCL type power output circuit, the first detector circuit or the second detector circuit controls the first detecting transistor or the second detecting transistor into an 'off' state, so that the switching means, such as a relay, is controlled into an open state.

Power output circuit

A monostable multivibrator circuit including a time constant circuit which includes a capacitor, an amplifier circuit which receives an output signal of the time constant circuit, and a positive feedback circuit which is connected between an output end of the amplifier circuit and an input end of the time constant circuit, characterized in that a trigger circuit is incorporated in a part of a circuit loop which is constructed of the time constant circuit, the amplifier circuit and the positive feedback circuit, the trigger circuit comprising an emitter-follower transistor which receives a feedback signal, another emitter-follower transistor which receives a trigger signal and whose emitter is connected to an emitter of the first-mentioned emitter-follower transistor in common, and a constant-current circuit which supplies a constant current to the emitters connected in common. Thus, the monostable multivibrator circuit can provide a predetermined pulse signal without any interference attributable to a trigger input circuit.

Monostable multivibrator and FM detector circuit employing differential

This invention discloses a monostable multivibrator which is useful for an FM detector circuit of a pulse count system. The monostable multivibrator has a time constant circuit which includes a capacitor, an amplifier circuit which receives an output of the time constant circuit, a positive feedback circuit which is connected between an output end of the amplifier circuit and an input end of the time constant circuit, and a trigger terminal which is disposed in a circuit loop constructed of the time constant circuit, the amplifier circuit and the positive feedback circuit; and is characterized in that the amplifier circuit is a differential amplifier which is made up of a pair of transistors connected in the differential form, the transistors being connected in common through emitter resistances connected in series with respective emitters thereof. Thus, the monostable multivibrator can provide pulse signals of a fixed pulse width without being influenced by noise.

Monostable multivibrator and FM detector circuit employing common

This invention relates to a monostable multivibrator which is operated in the non-saturated state. The monostable multivibrator circuit includes a time constant circuit which has a capacitor, an amplifier circuit which receives an output signal of the time constant circuit, a positive feedback circuit which is connected between an output end of the amplifier circuit and an input end of the time constant circuit, and a trigger terminal which is disposed in a circuit loop constructed of the time constant circuit, the amplifier circuit and the positive feedback circuit; and it is characterized in that the positive feedback circuit comprises a signal amplifying transistor which has a base receiving an output of the amplifier circuit and a collector supplying a signal to the time constant circuit, and a level clamp circuit which is coupled to the collector of the transistor in order to hold a collector output potential of the transistor higher than a base input potential thereof.

Monostable multivibrator circuit with clamped non-saturating common

The output derived from an electric circuit such as an OCL type power amplifier circuit is delivered to a load such as a speaker, through a switching means such as a relay. When the operation of the electric circuit has come out of a predetermined range of operation, the switching means is operated to break the connection between the electric circuit and the load. A detection circuit for detecting the operation of the electric circuit includes a detecting transistor constructed in a semiconductor integrated circuit. The detecting transistor is connected at its base to the input terminal for external connection of the semiconductor integrated circuit, so as to receive a signal representative of the operation state of the electric circuit. The detecting transistor is so biased as to allow a predetermined electric current to flow therethrough, when the electric circuit is operating within the predetermined range of operation. However, in case of a breakdown of the detecting transistor, or when the operation of the electric circuit has come out of the predetermined range of operation, the current flowing through the detecting transistor is changed from the predetermined level. This change is transmitted to a driving transistor which is adapted to break the switching means such as a relay.

Protective circuit

A trigger pulse forming circuit for converting a pulse signal into a trigger signal waveform is disclosed. It is characterized in that a time constant circuit is comprised in a collector output circuit of one of a pair of transistors for differential amplification and that a clamp circuit which employs a diode of the base-emitter path of a transistor is inserted between collector output circuits of the transistors for differential amplification. The input pulse signal to be subjected to the waveform conversion is impressed across the bases of the transistors for differential amplification, and the trigger pulse output signal is derived from the collector of the other of the transistors for differential amplification.

Pulse forming circuit

An input signal is applied to a first limiting amplifier circuit, and an output of the first limiting amplifier circuit is applied to a second limiting amplifier circuit. An output of the second limiting amplifier circuit is applied to a third limiting amplifier circuit. The output signal of the first limiting amplifier circuit is applied to a first detector circuit, the output signal of the second limiting amplifier circuit is applied to a second detector circuit, and the output signal of the third limiting amplifier circuit is applied to a third detector circuit. Bias means for stipulating the bias states of the first, second and third detector circuits are coupled to the third detector circuit. An output signal of the third detector circuit is applied to the second detector circuit as a bias signal, and an output signal of the second detector circuit is applied to the first detector circuit as a bias signal. An output signal of the first detector circuit exhibits a level corresponding to the sum among the output signals of the first, second and third limiting amplifier circuits.

Signal strength detecting circuit

A first intermediate frequency amplifier stage which executes the amplitude limiting operation of a double-converting FM tuner employing the integrated circuit technology is constructed in the form of an integrated circuit. An output signal of the first intermediate frequency amplifier stage is put into a square pulse waveform on the basis of the amplitude limiting operation, and therefore has higher harmonic components of high frequencies. When the higher harmonic components are injected into a second mixer circuit in a second frequency converter circuit, various higher harmonic components which have frequencies higher than a second intermediate frequency appear at the output of the second mixer conduit. When the higher harmonic components at the output of the second mixer circuit are injected into an FM demodulator circuit, beat trouble is induced. The second frequency converter circuit is also constructed in the form of an integrated circuit, and filter means to pass the fundamental waves of a first intermediate frequency signal and to reject the higher harmonic frequency components thereof is connected between the output of the first intermediate frequency amlifier stage executing the amplitude limiting operation and the input of the second mixer circuit, whereby the beat trouble can be prevented.

Double-converting FM tuner

An FM detector is constructed of a phase shift network and an analog multiplier. The analog multiplier includes a differential amplifier circuit and a phase detector circuit. The differential amplifier circuit includes differential pair transistors which are driven by FM intermediate frequency signals. A base emitter junction of a diode-connected transistor is connected across a base and an emitter of one of the differential pair transistors. The base of the one transistor and a base of the diode-connected transistor are connected to an emitter of an emitter-follower transistor, and the FM intermediate frequency signal is applied to a base of the emitter-follower transistor. Noise which develops in the base of the differential pair transistor or the base of the diode-connected transistor is reduced by the low output impedance of the emitter-follower transistor, so that the signal-to-noise ratio of the FM detector is improved.

In an FM stereo demodulator, a detector circuit for detecting a low supply voltage is used. The detection level of this detector circuit is made substantially equal to a supply voltage value at the time when the oscillation frequency of an oscillator circuit for reproducing a subcarrier signal begins to change. The stereo reproduction of the demodulator is compulsorily switched to monaural reproduction by an output from the detector circuit. As a result, the generation of an abnormal sound which is attributed to the beat between the reproduced subcarrier signal having fluctuated and a subcarrier signal component of a received broadcast signal is prevented.

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Kodaira, Japan

Masanori Ienaka