Pioneer Corporation

Pioneer Electronic Corporation

Masanori Hoshikawa

Hiroshi Kida

The present invention provides a video processor which has a simple circuit configuration and can scale up and down image resolution freely. A video signal processor includes a plurality of line memories, each storing one horizontal scanning line of video data series, a controller for controlling writing and reading operations of input video data series in the line memories for every horizontal scanning line, and an arithmetical unit for generating a new horizontal scanning line of video data series based on video data series from two line memories. The controller selects the vertical scaling power of the resolution, and generates a horizontal scanning synchronizing signal having a period depending on the selected scaling power. The arithmetical unit is triggered by the horizontal scanning synchronizing signal and generates a new video data series.

Video signal processor

An apparatus for enhancing the resolution of video data in a reduced scale of apparatus, and a video signal processing apparatus for freely setting the number of video data sequences for enhancing the resolution, is created from one horizontal scanning line portion of an incoming video data sequence, without changing the circuit configuration. The resolution enhancement processing apparatus stores every one horizontal line portion of each video data in an incoming video data sequence sequentially in a plurality of memories. A first video data group and a second video data group of horizontal scanning line portion of different scan periods are read repetitively N times within one horizontal scan period. The first video data group and the second video data group are mixed at varying mixing ratios to generate a video data sequence which has the vertical resolution enhanced by a factor of N.

Video signal processing apparatus with resolution enhancing feature

An apparatus for driving a display panel comprises a receiving circuit of a TV broadcasting wave. The writing and reading operations of the pixel data to/from the memory are performed synchronously with the self-advancing clock signal, thereby preventing a disturbance of a display image upon channel switching. The display driving apparatus according to another aspect of the invention has two frame memories to alternately store pixel data and a memory control apparatus to control the writing and reading operations to/from the frame memories which makes a scanning line interpolation processing apparatus constructed by a memory, an arithmetic operating circuit, and the like unnecessary. Furthermore, the driving apparatus can be altered to allocate storage in a memory for pixels which are to be displayed in one picture plane. This storage allocation allows a motion image and the still image to be simultaneously displayed.

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Yamanashi, Japan

Masanori Hoshikawa