Fujitsu Corporation

Masanori Higeta

Kenji Suzuki

Jun Kawahara

Hiroshi Nakayama

Seishi Okada

Hidekazu Osano

Takatsugu Sasaki

Kazuya Takaku

Hideyuki Sakamaki

Ryo Takata

An information processing apparatus includes: a first preprocessing arithmetic device configured to execute preprocessing for analog data from a first sensor; and a first post-processing arithmetic device connected to the first preprocessing arithmetic device and configured to execute post-processing for first preprocessed data, wherein the first preprocessing arithmetic device includes a first processor configured to: receive the analog data from the first sensor and convert the analog data into digital data; output feature data on the basis of a result of execution of feature extraction processing for the digital data; and output the feature data, and the first post-processing arithmetic device includes a second processor configured to: input the feature data; store the feature data in a first memory; and store, in the first memory, recognition result data based on a result of execution of recognition processing for the feature data.

Information processing apparatus, arithmetic processing device, and method of controlling information processing apparatus

An arithmetic processing device includes arithmetic processing units, each having a calculator unit; a scheduler that controls a push instruction to write data to a register file in one of the arithmetic processing units and a pull instruction to read data from the register file; a pull request bus to which the scheduler outputs a pull request and which is connected to the arithmetic processing units; a push request bus to which the scheduler outputs a push request and which is connected to the arithmetic processing units; and a pull data bus that inputs, into the scheduler, pull data read from the register file in response to the pull request. Each of the arithmetic processing units includes a pull data turn-back bus that propagates pull data read from its register file to the pull data bus.

Arithmetic processing device having multicore ring bus structure with turn-back bus for handling register file push/pull requests

An information processing system includes: a processor in one information processing apparatus among information processing apparatuses coupled via a ring bus corresponding to a closed-loop bus; and a first memory, wherein the processor: generate a verification request for verification of completion of a write request after issuing the write request to a second memory in the information processing apparatuses; transmit the verification request to a subsequent information processing apparatus; transmit, when a request from a preceding information processing apparatus is not a verification request, the request to the subsequent information processing apparatus; transmit, when the request is a verification request to another information processing apparatus, the verification request and a request to the first memory to the subsequent information processing apparatus in order of receiving; and execute, when the request is a verification request to the one information processing apparatus, processing and generate a response of completion of the processing.

Information processing system, information processing apparatus, and method for controlling information processing system

A memory controller includes: a determination part configured to determine a type of a DIMM having a different address line topology based on SPD; a slew rate setting part configured to set a slew rate of an address signal based on the type of the DIMM determined by the determination part; and a delay setting part configured to set a data delay amount when reading/writing data.

Memory controller and information processing apparatus

An information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, cause the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions.

Memory controller and information processing system for failure inspection

The optimization of a refresh cycle is carried out in harmony with the error occurrence state in the memory with the presence of a normal patrol controlling section controlling a normal patrol operation that patrols the memory; an additional patrol controlling section controlling an additional patrol operation that patrols, if a first error in the memory is detected during the normal patrol operation, an error occurring area in which the first error occurs and which is included in the memory; a measuring section () measuring, if a second error is detected in the error occurring area during the additional patrol operation, an error frequency representing information of error in the error occurring area; and a refresh cycle adjusting section adjusting the refresh cycle in accordance with the error frequency measured by the measuring section.

Memory refreshing circuit and method for memory refresh

A receiving apparatus includes a first receiving circuit that receives an input signal based on a clock signal, and outputs a first output signal, a second receiving circuit that receives the input signal based on the clock signal, and outputs a second output signal, and a comparison circuit that compares value of the first output signal outputted by the first receiving circuit and value of the second output signal outputted by the second receiving circuit.

Receiving apparatus, transmission apparatus, and transmission method

A transmission method for transmitting information between a transmission device and a reception device, the method includes determining whether or not an error is detected in information from the transmission device, requesting the transmission device to re-transmit the error-detected information when an error is detected, re-transmitting information corresponding to a re-transmission request as re-transmission information from the transmission device when the re-transmission request is detected, registering the re-transmission information as a test pattern, transmitting the registered test pattern to the reception device, registering the re-transmission data received from the transmission device as a collation pattern, reading out the collation pattern corresponding to the received test pattern, and collating the test pattern and the collation pattern when a test pattern is received from the transmission device, and adjusting and setting a parameter of the reception device on the basis of a pattern collation result.

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Kawasaki, Japan

Masanori Higeta