Fujitsu Corporation

Masanori Doi

Iwao Yamazaki

Tsuyoshi Motokurumada

Masahiro Doteguchi

A calculator includes a main TLB that stores therein a plurality of address translation pairs indicating a correspondence of a virtual address and an absolute address as a page table and a micro TLB that stores therein part of the page table stored in the main TLB. In the micro TLB, a TLB virtual address [63:13] and a TLB absolute address [46:13] are registered in a correlated manner. With such configuration, when registering an address translation pair in the micro TLB, the calculator chops the address translation pair to a page size of a first size or a fourth size to register it in the micro TLB. Upon receiving an address translation request, the calculator searches for an address corresponding to the page size of the first size or the fourth size registered in the micro TLB, so that address comparison conditions can be reduced, enabling to improve a processing performance.

Calculator and TLB control method

A memory control apparatus includes a reading unit, an inserting unit, an identifying unit, a determining unit, and an outputting unit. The reading unit reads data from the memory. The inserting unit inserts a dummy error at an insertion position in the data thereby obtaining error data. The identifying unit identifies an error position at which an error has occurred in the error data. The determining unit determines whether the insertion position matches the error position. When the insertion position matches the error position, the outputting unit outputs corrected data obtained by correcting an error at the error position.

Method and apparatus for controlling memory

Context information pertaining to the virtual address is obtained, and a storage location for storing the address translation information is determined based on the context information.

Address translation information storing apparatus and address translation information storing method

A method for controlling an address conversion buffer, constituted on a processor capable of executing a plurality of threads simultaneously on one core, includes registering address conversion information in an entry of the address conversion buffer that includes a first memory area usable by one of the threads and a second memory area shared among all the threads, allocating a part of the second memory area as a swap area of the first memory area, and transferring data in the swap area to the first memory area, based on thread switching executed by the processor.

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Kawasaki, Japan

Masanori Doi