Fujitsu Corporation

Victor Company of Japan, Limited

Fujitsu Vlsi Limited

Masanobu Yoshida

Takao Akaogi

Yasushi Kasa

Shouichi Kawamura

Yasushige Ogawa

Kiyoshi Itano

Nobuaki Takashina

Mitsuo Higuchi

Hirokazu Yamazaki

Kiyonori Ogura

Takuya Kakinuma

Kohichi Maeda

Manabu Tsuchida

Yasushige Oqawa

Hideo Oura

Hideyuki Wakimoto

A liquid crystal display device includes a first substrate having a plurality of pixel electrodes formed thereon in a matrix fashion, a second substrate having a common electrode formed thereon as facing the pixel electrodes with a specific gap, a liquid crystal filled in the gap, and a multi-layered optical film formed on the pixel electrodes. The multi-layered optical film has a first optical film that exhibits a first refractive index, a second optical film formed on the first optical film, the second optical film exhibiting a second refractive index higher than the first refractive index, and a third optical film formed on the second optical film, the third optical film exhibiting a specific resistance ranging from 1&#xd7;10&#x3a9;cm to 8&#xd7;10&#x3a9;cm.

Liquid crystal display device and liquid crystal display apparatus using liquid crystal display device

A semiconductor memory device includes a first memory cell consisting of a single-gate transistor and a stacked-gate transistor and a second memory cell consisting of a stacked-gate transistor, and is constructed such that a memory cell array composed of the first memory cells and a memory cell array composed of the second memory cells share peripheral circuits.

Semiconductor memory device adapted for large capacity and high-speed

An electrically erasable programmable nonvolatile semiconductor memory has a memory cell array having a plurality of memory cells which are placed as a matrix configuration. The memory cell array is divided into a plurality of memory cell blocks having required sizes by splitting each bit line of the memory cell array at: an optional position. This memory provides a dual operation function without complicating the circuit thereof or increasing the chip size thereof. The bit structure of each memory cell block to be divided from the memory cell array is variable.

Electrically erasable programmable nonvolatile semiconductor memory

A semiconductor device has a function of reading device information specific to the device as and when required. The semiconductor device has storage units for storing plural pieces of device information and a selector for selecting a predetermined one of the information pieces stored in the storage units when a device information read mode is set, so that the read information may match device data such as a manufacturer name and part name printed on the semiconductor device.

Semiconductor device with selectable device information

A nonvolatile semiconductor memory apparatus of a reference type is provided with a memory circuit, reference circuit and differential amplifier. A drain current of a reference cell transistor is formed such that it becomes almost half a drain current of a memory cell transistor, thereby enabling the memory circuit to be in symmetric relation with the reference circuit. Therefore, a parastic capacitance in the memory circuit is made to be almost the same as that of the reference circuit, and thus a difference in noise level between a noise input to one input of the differential amplifier and a noise input to the other input of the differential amplifier is made to be almost zero, thereby speeding up the data read-out operation of the semiconductor memory apparatus.

Nonvolatile semiconductor memory apparatus

A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (Vcc), the gate of the transistor being connected to a low source voltage (Vss) to provide an internal source voltage (Vci), a combination of an arrangement for dropping the external source voltage (Vcc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (Vpp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (Vref) as a lower threshold (Vth) allowed for cell transistors (11.sub.00 to 11.sub.22), and comparing the voltage of a data bus (13) with the reference voltage (Vref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

Nonvolatile semiconductor memory

A semiconductor memory having address buffer means, memory cell means, word line selection means, bit line selection means, an output buffer, first address generation means connected to the address buffer means, for providing and address for specifying a group of data pieces, and second address generation means for providing addresses for specifying the data pieces, respectively, the semiconductor memory comprising first reading means for selecting and reading a group of data pieces through one of the word line selection means and bit line selection means according to an address provided by the first address generation means, second reading means for selecting the data pieces, which have been selected and read according to the address provided by the first address generation means, through one of the bit line selection means and word line selection means according addresses provided by the second address generation means and providing them to the output buffer; and pre-reading means for reading another group of data pieces according the another address to be provided by the first address generation means while the preceding data pieces are being read according to the preceding address provided by the first address generation means and being selectively provided to the output buffer according to the addresses provided by the second address generation means.

Nonvolatile semiconductor memory with pre-read means

When a current flows through a selected memory cell transistor at the time of data reading, the gate voltage of an n-channel MOS transistor, which makes up the current flowing through the load, rises. Thus, when a current flows through a selected memory cell transistor at the time of data reading, the current through the load is increased so that the time required for data reading when the current flows through the selected memory cell transistor can be shortened and the data reading can be effected at a high speed.

A nonvolatile semiconductor memory employs sense amplifiers, circuits for providing stabilized source voltages, and circuits for realizing high-speed and reliable read and write operations. The semiconductor memory has a matrix of nonvolatile erasable memory cell transistors. The semiconductor memory employs an arrangement for effectively using a plurality of source voltages and applying a verify voltage to sense amplifiers and word lines, a write verify arrangement for detecting an output of the sense amplifiers, an arrangement for comparing an output of the sense amplifiers with a reference value to determine whether or not a written state of the memory cell transistors is acceptable, an arrangement for adjusting an output of the sense amplifiers with use of inverters and transistors in response to a current flowing to the memory cell transistors, to improve a drive speed of the sense amplifiers, an internal source voltage generating arrangement using an n-channel depletion transistor connected to an external source voltage (V.sub.CC), the gate of the transistor being connected to a low source voltage (V.sub.ss) to provide an internal source voltage (V.sub.ci), a combination of an arrangement for dropping the external source voltage (V.sub.cc) for read to a predetermined value to drive a read circuit in the memory and an arrangement for dropping an external voltage (V.sub.pp) for write, to generate a word line potential for a verify-after-write operation, an arrangement for setting a reference voltage (V.sub.ref) as a lower threshold (V.sub.th) allowed for cell transistors (11.sub.00 to 11.sub.22), and comparing the voltage of a data bus (13) with the reference voltage (V.sub.ref), to simultaneously carry out an erase-verify operation on all memory cell transistors, and a pre-read arrangement for accessing the next address during a read time of the sense amplifiers, to improve a read speed.

An electrically programmable and electrically erasable non-volatile semiconductor memory device having an array of single transistor cells is provided. The disclosed device protects against reading faults even in the event that adjacent transistors may be over erased. Each of the cell transistor rows has an associated word line and an associated select element. The select elements are connected to the sources of their associated cell transistors and are arranged to activate those cell transistors only when their associated word line is selected. Cell transistors in unselected rows are not activated and thus do not interfere with reading even if they are in an over erased condition.

EEPROM and EEPROM reading method

An erasable non-volatile semiconductor memory device has a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detects the write status of each memory cell by a differential type detection circuit through first and second bit lines connected to the two cell transistors. Further, the erasable non-volatile semiconductor memory device sets all cell transistors constructing a plurality of the memory cells to the erasing status or write status in entirety, and controls the connection of the first and second bit lines for executing the read/write test. Therefore, the erasable non-volatile semiconductor memory device according to the present invention can reduce the erasing process cycles, which requires a long time, falsely read out the '0' data and '1' data without writing actual data into each memory cell to shorten the test time, and thus can supply a low price product.

Frasable non-volatile semiconductor memory device having read/write test

A semiconductor device for absorbing a noise comprises a first and second buffer. The first and second buffers receive an external signal having a rising edge and a falling edge, and performs waveform shaping thereof to produce an output signal. The first buffer, which issues an output signal for controlling the internal circuits of a chip of the semiconductor device so as to make the chip's internal circuits active/stand-by, is not sensitive to the rising edge of the external signal, but is sensitive to the falling edge of the same external signal. The second buffer, which issues an output signal for controlling an output circuit of a chip of the semiconductor device so as to make the output circuit active/stand-by, is sensitive to both the rising and the falling edges of the external signal.

Semiconductor device for preventing malfunction caused by a noise

A NAND gate circuit which can be used for a decoder circuit, includes a high potential voltage source (V.sub.cc), an output terminal (V.sub.OUT), and a load element (T.sub.1) connected between the high potential electric voltage source (V.sub.cc) and the output terminal (V.sub.OUT). A driving circuit is serially connected with the output terminal (V.sub.OUT), and a low potential voltage source (V.sub.ss), and has a plurality of driving transistors (T.sub.2, T.sub.3) which are serially arranged. An input signal is applied to each gate. At least one transistor, constituting the driving circuit, has a driving performance different from the other transistors of the driving circuit. An ideal NAND gate circuit can be provided in which erroneous operation due to noise can be effectively prevented by setting the input threshold voltage to a constant voltage no matter what the combination of the input signals.

Nand gate circuit

A power supply potential rising detection circuit comprises a transistor having a control gate and a floating gate, connected in series with a load element between first and power supply terminals. A first potential is applied to the control gate, the first potential being dependent on the power supply potential at the first power supply terminal. A switching element is operatively connected to the floating gate and controlled by a second potential dependent on the power supply potential, and reduces the potential of the floating gate and turns off the transistor when the power supply potential reaches a predetermined value, thereby outputting a power supply potential rising detection signal from the series connection point between the load element and the transistor.

Growing community of inventors

Kawasaki, Japan

Masanobu Yoshida