Matsushita Electric Industrial Co., Ltd.

Masanobu Mizuno

Hiroshi Takahashi

Michiaki Muraoka

Toshiyuki Yokoyama

Makoto Fujiwara

Yuji Takai

Miwaka Takahashi

Katsuya Fujimura

Kazuyoshi Takemura

Kasumi Hamaguchi

Kaoru Okazaki

Sadashige Sugiura

An IP database includes a system level IP used in system level design. IPs A and B in the system level IP are divided into processing algorithm description portions, input data structure definition portions and output data structure definition portions. When a communication channel is provided between the IPs communicating data in architecture or functional design, a conversion circuit generating means generates a data conversion circuit between the communication channel and each of the IPs with reference to the IP database.

IP base LSI designing system and designing method

A database for design of an integrated circuit device having data stored therein in a flexibly utilizable state, and a method for designing an integrated circuit device using such a database. A virtual core database (VCDB) for storing design data and a VCDB management system (VCDBMS) as a control system are provided. The VCDB includes virtual core (VC) clusters, test vector clusters, and purpose-specific function testing models. The VCDB also includes a system testing database having shared test clusters and peripheral model clusters. The VCDBMS includes a function testing assist section for generating test scenarios, the purpose-specific function testing models, system testing models, and the like, a VC interface synthesis section, and the like.

Database for design of integrated circuit device and method for designing integrated circuit device

A database includes: a virtual core (VC) cluster, on which data needed in designing various components of an integrated circuit device is separately stored at least on a specification VC and a register-transfer-level VC (RTL-VC); and implementability evaluation information stored on the specification VC. The information represents performance of the RTL-VC in accordance with a specification defined by the specification VC in the VC cluster. Specification VCs, corresponding to those components, are entered, and then the integrated circuit device being designed using the specification VCs entered has its implementability evaluated by reference to the implementability evaluation information stored on the specification VCs. In this manner, it is possible to determine, at a higher level of a design process, whether or not the respective VCs can meet the required performance easily. Thus, a needless, lengthy exploration of multiple architectural choices or a design deadlock, which usually results from overly rigorous requirements, is avoidable.

Database for designing integrated circuit device, and method for designing integrated circuit device

A database, in which data is stored in a flexibly usable state, is provided for use in the design of an integrated circuit device, and a method for designing an integrated circuit device using such a database is also provided. A design environment includes: a virtual core database (VCDB), which is hierarchical design data storage; and a virtual core database management system (VCDBMS) as a control system. The VCDB includes architecture information and a VC cluster. The VC cluster includes: a specification VC for storing therein data at a specification level; an architecture VC for storing therein data at an architectural level; an RTL-VC for storing therein data at a register transfer level; and a performance index used for evaluating the performance of the respective VCs. By providing these VCs for respective layers, new VCs can be generated, data within the VCs can be modified and instances can be generated at the respective levels. As a result, the data can be used flexibly and recycled as well.

In a design process of an integrated circuit system, an interface model is generated between a behavioral model described at a behavioral level and an RTL model connected to the behavioral model. The interface model includes protocol converter, bit precision converter and signal converter. The protocol converter converts the protocol of the behavioral model, from which the concept of &ldquo;clock&rdquo; is absent, into that of the RTL model to time the behavior represented by the behavioral model with clock pulses for the RTL model. The bit precision converter converts the decimal point representations or bit widths of input/output data. And the signal converter converts signal lines or signal values for an input/output signal of the behavioral model. By providing an interface model like this, the overall system can have its design verified.

Method of design verification for integrated circuit system and method for generating interface model for design verification

A simulator capable of counting a number of events occurring in each of functional modules constituting an LSI and calculating an index value for selecting a simulation method for each functional module in simulation of an operation of the LSI with a first test vector set. The simulator further capable of selecting one simulation method among a plurality of simulation methods for each functional module based on the selection index value, and of controlling execution of simulation of the LSI operation with a second test vector set in the simulation method selected for each functional module.

Simulator and computer-readable recordable medium having program for execution on computer realizing the simulator recorded thereon

A simulation executing unit includes a conversion unit and a simulation portion. The conversion unit includes a circuit dividing portion, a circuit converting portion and a converted logic circuit generating portion, and the circuit dividing portion divides a logic circuit into combinational partial circuits each interposed between registers or between a register and an input pin or the like. The circuit converting portion generates, on the basis of the divided combinational partial circuits, a converted logic circuit by modifying allocation of registers included in the logic circuit, so as to decrease the number of registers included in the logic circuit without changing the output timing of the logic circuit. The simulation unit performs a simulation on the converted logic circuit.

Simulator of logic circuit and simulation method

Test vector storing means outputs data for simulation at a predetermined transfer speed. A signal processor executes the simulation of a digital signal processing circuit by using the data for simulation and outputs the simulation result. Simulation result storing means stores the simulation result input at a predetermined transfer speed. Simulation program generating means generates a simulation program, in advance, which is executed by the signal processor and has throughput that is coincident with the output speed of data of the test vector storing means. Synchronizing means synchronizes the data transfer of the test vector storing means, the execution speed of the signal processor, and the data transfer of the simulation result storing means.

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Osaka, Japan

Masanobu Mizuno