Mitsubishi Denki Kabushiki Kaisha

Masanobu Kohara

Hiroshi Shibata

Masatoshi Yasunaga

Mitsuyuki Takada

Tetsuo Tada

Shin Nakao

Takashi Kondo

Eishi Gofuku

Ryoichi Takagi

Yoshiyuki Morihiro

Yomiyuki Yama

Tsuneo Hamaguchi

Ryouichi Takagi

Kenji Kagata

Mitsumasa Mori

Tosihiro Fusayasu

Isao Kitamura

Hirotugu Yamada

Kurumi Miyake

The semiconductor package and manufacturing method thereof whereby the inexpensive package of high thermal conductivity is obtained by applying a Cu/Mo/Cu clad material for a base plate which matches the thermal expansion of a semiconductor chip, and the inexpensive package with high heat transfer suitable for a high frequency device is obtained by controlling a thickness of glass, and a size of a lead (width, thickness), thereby to match impedance of a wiring portion with that of the semiconductor chip, by plating only necessary areas with Au, and by plating the exterior with Sn.

Cu/Mo/Cu clad mounting for high frequency devices

This invention relates to printed circuit boards and a method of fabricating same wherein the input/output terminals are integral with the wiring layer of the printed circuit board. This arrangement allows for a higher density of input/output connections than is possible with conventional printed circuit boards.

Printed circuit board provided with a higher density of terminals for

Disclosed herein is a wiring panel constructed with a substrate; an electrically conductive member laminated on the substrate and principally composed of copper; and an insulating member composed of an organic substance, wherein a very small amount of a non-metallic element is incorporated into the electrically conductive member, and a very small amount of a metal element is incorporated into the insulating member. Also disclosed herein is a method for producing a wiring panel constructed with a substrate, an electrically conductive member provided on the substrate and composed of copper as the principal constituent, and an insulating layer of an organic substance covering the conductive member, which comprises steps of: applying onto the surface of the electrically conductive member a surface-reforming layer which functions to suppress electron transfer through the surface of the electrically conductive member, and thereafter forming the organic insulating layer on the electrically conductive member.

Wiring panel including wiring having a surface-reforming layer and

A lead frame includes a die pad for mounting thereon a semiconductor chip having a plurality of electrodes, a plurality of leads for electrical connection with the plurality of electrodes of the semiconductor chip, an outer frame disposed on the periphery of the die pad for supporting the die pad and the plurality of leads, and a resin guide portion extending to the vicinity of the die pad from the outer frame for guiding a molten resin over and under the semiconductor chip during resin packaging. A semiconductor device manufacturing method includes mounting a semiconductor chip having electrodes on a substrate having a resin guiding portion for guiding a resin over and under the semiconductor chip during resin packaging; electrically connecting leads on the substrate to the electrodes positioning the semiconductor chip and the substrate between a pair of mold halves injecting a molten resin into the mold and solidifying the resin.

Method for manufacturing a resin encapsulated semiconductor device

A package body for accommodating a semiconductor chip includes a plurality of inner-electrodes disposed on the package body and arranged in a multiplicity of rows around the semiconductor chip and outer-electrodes in the package body electrically connected to the corresponding inner-electrodes. The package body includes support sections disposed on the package body between the rows of inner-electrodes for supporting metal wires which connect the inner-electrodes to the electrodes of the semiconductor chip. A conductive layer for diminishing the floating capacitance between the metal wires may be included in the support sections.

Semiconductor device and package

A test apparatus for a semiconductor device is provided to be used for testing, wafer by wafer, a semiconductor device formed on a semiconductor wafer. The test apparatus for a semiconductor device comprises a test head, a probe card and a selection circuit. The probe card has an insulating transparent base plate, and protruding parts are formed on the main surface of the base plate corresponding to electrode pads on a test object semiconductor wafer, and conductive layer forming a prober for the electrode pad is formed on the surface of each of these protruding parts. A wiring layer is formed on the surface opposite to the main surface. The wiring layer and the probers are connected electrically through the through holes provided on the base plate. A prober to be connected to the test head is switched electrically, which makes it possible to test a semiconductor device without moving the corresponding semiconductor wafer.

Probe plate used for testing a semiconductor device, and a test

A lead frame includes a die pad for mounting thereon a semiconductor chip having a plurality of electrodes, a plurality of leads for electrical connection with the plurality of electrodes of the semiconductor chip, an outer frame disposed on the periphery of the die pad for supporting the die pad and the plurality of leads, and a resin guide portion extending to the vicinity of the die pad from the outer frame for guiding molten resin over and under the semiconductor chip during resin packaging. A semiconductor device manufacturing method includes mounting a semiconductor chip having electrodes on a substrate having a resin guiding portion for guiding a resin over and under the semiconductor chip during resin packaging; electrically connecting leads on the substrate to the electrodes; positioning the semiconductor chip and the substrate between a pair of mold halves injecting a molten resin into the mold to fill the cavity; and solidifying the resin.

Lead frame and semiconductor device

A probing plate for wafer testing is provided with a plurality of probes arranged so as to correspond to a plurality of bonding pads of semiconductor devices fabricated on a semiconductor wafer. The probing plate has a base plate formed of an insulating material, such as a photosensitive glass, and has contact fingers each having a raised portion in the free end thereof, contact conductors respectively formed on the surfaces of the raised portions of the contact fingers so as to be brought into contact with the corresponding bonding pads, and wiring conductors formed in a predetermined pattern on the surface of the base plate so as to extend respectively from the contact conductors. The contact conductors and the wiring conductors are formed simultaneously by a photolithographic process. The contact fingers and the raised portions thereof are also formed by subjecting the base plate to a photolithographic process. Forming the contact conductors over the surfaces of the raised portions of the contact fingers prevents accidental contact of the contact conductors with the bonding pads of semiconductor devices other than the objective semiconductor devices.

Probing plate for wafer testing

A semiconductor device provided with a semiconductor chip having first and second surface facing in the opposite directions, electrodes on the first surface; a plurality of leads disposed parallel with each other along the second surface of the semiconductor chip and each having opposite ends respectively extending outward from opposite sides of the second surface; a wire electrically connecting one end of each lead and one of the electrodes of the semiconductor chip; a resin enclosing the semiconductor chip, the ends of the leads connected to the electrodes, and the wires. The leads extend across the second surface of the semiconductor chip so that a relatively long length each lead embedded in the resin and the wire bonding portions of the leads are located in the vicinity of the sides of the semiconductor chip, thereby improving the releability of the device and the ease of to wire bonding.

Semiconductor device

The electronic device relating to the invention is that in which an electrode is formed on the rear side surface of a semiconductor element, a circuit wiring and an external electrode connected electrically to one end of the circuit wiring are formed on the rear side surface of a flexible insulating film with a first opening provided therefor, a lead terminal overhanging to the first opening is connected electrically to the other end of the circuit wiring, a second opening is formed on the flexible insulating film so as to expose a part of the external electrode, a package substrate is constituted of the flexible insulating film in tape assembly system, the circuit wiring, the external electrode and the lead terminal, the semiconductor element is disposed on the rear side surface side of the flexible insulating film under the first opening and the lead terminal is connected electrically and mechanically thereto, a part or the whole of the semiconductor element, the electrode, the lead terminal, a part of the circuit wiring and the first opening are sealed with a sealing resin, a semiconductor device is constituted of the semiconductor element, the electrode, the package substrate and the sealing resin, the semiconductor device is mounted in a recession formed on the front side of a thin flexible substrate like IC card so as to make the front side surface of the flexible insulating film coincide with the front side surface of the thin flexible substrate.

Electronic device

A semiconductor memory device including a MOS transistor having source and drain electrodes formed on a surface of a semiconductor substrate; an insulating layer formed on a surface of the semiconductor substrate; a first conductive layer which is connected to the source or drain electrodes and is extended on the surface of the insulating layer through the insulating layer; a dielectric layer formed on the surface of said first conductive layer; and a second conductive layer formed on the dielectric layer opposite the first conductive layer, wherein the first conductive layer, the dielectric layer and the second conductive form a capacitor for a memory element.

Semiconductor memory device having a mos transistor and superposed

A heat dissipating member including a heat sink is placed on a module base board with flip-chips mounted thereon, with metallic plates and first adhesive materials of a good thermal conductivity interposed between the heat dissipating member and the flip-chips in a close contact relation and with a second adhesive material interposed between the heat dissipating member and the base board, wherein the first adhesive material is selected to have a melting point lower than that of the second adhesive material, and then such an assembly is heated so that both the first and second adhesive materials are melted and the metallic plates are mounted onto the flip-chips and the heat dissipating member is mounted onto the base board. A gap is formed between the metallic plates and the heat dissipating member as a result of earlier solidification of the second adhesive material than that of the first adhesive material so as to be precisely controlled such that a heat transferring effect therebetween may not be degraded.

Growing community of inventors

Itami, Japan

Masanobu Kohara