Nec Corporation

Nippon Telegraph and Telephone Corporation

Masanobu Arai

Masaru Yamaguchi

Takenori Ogata

Junji Yamato

Akira Tomono

Kyoko Sudo

Masahiro Imamura

Satoru Yamano

Shin'ichi Koike

Takao Hayashi

Takashi Shinozuka

Yoshihide Hiraoka

Noriaki Edasawa

A radio communication method, a radio communication system and a wireless terminal by which low power consumption and the flexibility of a network can be realized. A base station and wireless terminals change an intermittent receive period and the preamble length of data on the basis of characteristics of the multihop radio network to carry out the intermittent receiving of data. Thus, a wireless terminal relaying data can receive the data reliably and a useless boot-up of a receiving part and standby time can be largely reduced to achieve low power consumption.

Radio communication method, radio communication system and wireless terminal

Packets are accumulated in a packet transmission memory, and the data bits stored in each packets are serially output from the packet transmission memory, wherein an internal bit address signal is sequentially changed in the packet transmission memory so as to store the serial data bits in an addressable data storage region without any serial-to-parallel data conversion, and the data bits are serially output from a built-in parallel-to-serial data converter connected to the data storage regions, thereby making the circuit arrangement simple.

Memory used in packet switching network for successively storing data bits in data storage region and serially outputting data bits and method used therein

According to the present invention, two-dimensional pressure distribution associated with walking are collected at a preselected time interval as time series pressure distribution images, superposed images are formed by superposing the time series pressure distribution images in a time direction, a plurality of foot pressure mass regions are extracted from the superposed images, correspondence of each foot pressure mass region to the time series pressure distribution images are detected, feature parameters associated with the walking are detected based on the correspondence, and the feature parameters are displayed or printed.

Walking pattern processing method and system for embodying the same

A phase-locked loop circuit has a ring oscillator comprising a plurality of 1st, 2nd, . . . , nth inverter chains composed of series-connected 21, 22, . . . , 2n inverters (n.gtoreq.2), respectively, an (n+1)th inverter chain composed of an odd number of series-connected inverters, and a plurality of 1st-nth selectors associated with the 1st-nth inverter chains, respectively, for selectively outputting input signals to and output signals from the 1st-nth inverter chains, the 1st-nth inverter chains being combined respectively with the 1st-nth selectors in respective combinations, the combinations and the (n+1)th inverter chain being connected in a ring configuration. A phase comparator compares an input clock signal and an oscillated clock signal from the ring oscillator in phase, and applies an output signal to a control circuit which controls the 1st-nth selectors to synchronize the oscillated clock signal with the input clock signal.

Phase-locked loop circuit having ring oscillator

A push-pull-type amplifier circuit has three current mirror circuits CM1, CM2, CM3 and transistors M6, M7 connected between a reference current supply I.sub.R and output transistors M2, M3 for controlling an idling current flowing through the output transistors M2, M3 so as to be proportional to a current flowing through the reference current supply I.sub.R so that the idling current will be stabilized irrespective of variations in a power supply voltage. An operational amplifier which incorporates the push-pull-type amplifier circuit as an output stage circuit is highly stable in operation, and can be designed in a simple arrangement without having to take into account power supply voltage variations.

Push-pull-type amplifier circuit

A subscriber line interface circuit includes a switched hybrid circuit operable during a POTS mode when the associated subscriber is using a POTS station and in an ISDN mode when the subscriber is using an ISDN station. The hybrid circuit includes a first amplifier circuit for coupling a signal at the two-wire port thereof to its four-wire transmit port, and a second amplifier circuit for coupling a signal at the four-wire receive port of the hybrid to the two-wire port. A high termination impedance is synthesized at the two-wire port during the POTS mode and a low termination impedance at the two-wire port during the ISDN mode. The signal from the four-wire transmit port is converted to a digital signal and applied to a digital signal processor which is configured differently according to DSP running programs respectively stored in first and second memories for operations during the POTS and ISDN modes. The DSP processes signals received from the hybrid's four-wire transmit port as well as from the telephone switching system according to the program supplied from the first or second memory and applies the process signals to the switching system and the four-wire receive port.

Subscriber line interface circuit for serving ISDN subscribers using

A tone signal detecting circuit includes a sampling circuit, a storage circuit, and a comparing circuit. The sampling circuit samples a tone signal at a sampling rate N times (N is a natural number) higher than a frequency f of the one signal. The storage circuit stores M (M is a natural number) latest values of time series data from the sampling circuit. The comparing circuit compares a plurality of polarity patterns expected on the basis of a tone signal with polarity patterns stored in the storage circuit and outputting coincidence outputs.

Tone signal detecting circuit

A clock jitter suppressing circuit includes a control circuit, a delay circuit, and a selection circuit. The delay circuit sequentially delays a clock signal at time intervals sufficiently shorter than the period of the clock signal. The selection circuit selects and outputs one of delay outputs from the delay circuit which is determined in accordance with a selection signal. The control circuit generates a selection signal for selecting a predetermined delay output when no jitter is caused in the clock signal. Every time jitter is caused in the clock signal, the control circuit generates a selection signal for selecting a delay output which is shifted by an amount corresponding to the phase amount of the jitter in a direction to cancel a polarity of the jitter.

Clock jitter suppressing circuit

In a baude rate sampling type receiving circuit for use in a system for transmitting digital data signal at a transmission baude rate, in order to control the sampling phase at the optimum phase, desired elements of an autocorrelation function of a series of baud rate sampled signals are calculated and are linearly summed by a calculating circuit to provide a linear summation as a power of the series of sampled signals. The sampling phase at the baud rate sampling is controlled by a control circuit by use of the linear summation so that the power is maximized, whereby the sampling phase is maintained at the optimum sampling phase.

Digital signal receiving circuit with means for controlling a baud rate

The whole or part of a waveform is cancelled by a circuit comprising a nonrecursive filter and a recursive filter. The nonrecursive filter has a plurality of first multipliers having first tap weights for modifying symbols successively shifted along a shift register. The recursive filter is connected in a series circuit to the shift register and has a second tap weight for recursively modifying the output of the shift register. The recursively modified symbol is modified by a second multiplier having a third tap weight and combined in an adder with the symbols modified by the first tap weights to produce a replica of an undesired waveform. The replica is destructively combined in a subtractor with an incoming symbol having an undesired waveform. The output of subtractor is utilized to derive the tap weights to adaptively control the inputs to the adder.

Circuit for cancelling whole or part of a waveform using nonrecursive

In a receiver comprising a filter section for filtering a transmitted digital signal into a filtered digital signal and an equalizer section for equalizing the filtered digital signal into an equalized digital signal as a reproduced digital signal in response to controllable tap gains supplied from a control arrangement, the equalizer section comprises a first arrangement for filtering the filtered digital signal in response to predetermined ones of the controllable tap gains to produce an intermediate digital signal and a second arrangement for equalizing the intermediate digital signal into the equalized digital signal in response to remaining ones of the controllable tap gains except for the predetermined controllable tap gains to produce the reproduced digital signal. The control arrangement controls the predetermined tap gains so as to minimize noise power of a noise signal accompanying the filtered digital signal and the remaining controllable tap gains and to equalize the intermediate digital signal into the equalized digital signal.

Receiver capable of improving signal-to-noise ratio in reproducing

An echo canceller for bidirectional transmission on two-wire metallic subscriber lines in an integrated service digital network employing a filter positioned in the echo path having the property that a zero point is located so as to cancel the echo path transfer function attributable to the inductance component of the line coupling transformer.

Echo canceller for bidirectional transmission on two-wire subscriber

A subscriber line interface circuit comprises a balanced amplifier having positive and negative inputs for amplifying a voltage thereacross to generate a pair of mutually complementary voltages across true and complementary outputs. Four resistors of a first value are respectively connected between a subscriber tip line and the negative input, between a subscriber ring line and the positive input, between the negative input and true output and between the positive input and complementary output. Two resistors of a second value smaller than the impedance of the subscriber loop are respectively connected between the tip line and the complementary output and between the ring line and the true output. A DC feedback circuit is connected to the complementary output to generate a DC feedback signal according to a desired variable DC power feeding characteristic. An AC feedback circuit generates an AC feedback signal proportional to a differential voltage across the tip and ring lines and inversely proportional to a desired AC impedence. The DC and AC feedback signals are combined in a circuit which supplies to the negative input a current corresponding to the combined signals.

Subscriber line interface circuit having means for combining DC and AC

In a subscriber line interface circuit of a telephone switching system, a differential amplifier (1) is coupled through the line terminals (T, R) of a two-wire subscriber line for detecting a voltage difference developed thereacross. First and second resistances (8, 9) of equal values are coupled at their first ends to the line terminals, respectively. Tip and ring drivers (2, 3) are connected to the other end of first and second resistances for driving the load impedance of the subscriber line. First, second and third feedback loops (f.sub.1, f.sub.2, f.sub.3) are provided, the first feedback loop being coupled from an output of differential amplifier (1) to the input of the drivers (2, 3) vary the impedance characteristics of the first and second resistances (8, 9) so that a high impedance is synthesized across each of the first and second resistances. The second and third feedback loops are also coupled from the output of differential amplifier (1) to the drivers (2, 3), each of the second and third feedback loops having a different passband frequency characteristic and having the effect of reducing the synthesized impedances to a predetermined value.

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Tokyo, Japan

Masanobu Arai