Kyocera Corporation

Masanao Kabumoto

Masaaki Hori

Tetsuo Hirakawa

Masaru Nomoto

Kouki Kawabata

Shigeto Takeda

Yoshihiro Nabe

A multi-layer wiring board comprises an insulating substrate having, on a central part of its top surface, a semiconductor device mounting portion and having, on its under surface, an external electrode. The insulating substrate includes a multilayered wiring having a first group of parallel wiring lines; a second group of parallel wiring lines arranged orthogonal thereto; and a group of through conductors for providing electrical connection therebetween. Power is supplied from the external electrode to the semiconductor device through built-in capacitors formed therewithin. The built-in capacitors are connected in parallel that have different resonance frequencies within a range from an operating frequency band for the semiconductor device to a frequency band for a harmonic component, and at an anti-resonance frequency occurring between the different resonance frequencies, a composite impedance is equal to or below a predetermined value.

Multi-layer wiring board

A multilayered wiring board comprising a first stacked structure consisting essentially of a first insulating layer having a first parallel conductor array and a second insulating layer formed thereon, having a second parallel conductor array oriented orthogonal to the first parallel conductor array, the first and second parallel conductor arrays being electrically interconnected by a first through conductor array; and a second stacked structure consisting essentially of a third insulating layer having a third parallel conductor array crossing at an angle of 30 to 60 degrees to the first parallel conductor array and a fourth insulating layer formed on top of the third insulating layer, having a fourth parallel conductor array orthogonal to the third parallel conductor array, the third and fourth parallel conductor arrays being electrically interconnected by a second through conductor array, wherein the second stacked structure is overlaid on the first stacked structure by interposing therebetween an intermediate insulating layer having a conductive layer, and the first or second parallel conductor array and the third or fourth parallel conductor array are electrically interconnected by a third through conductor array.

Multilayered wiring board

A semiconductor element-housing package, comprising an insulating substrate composed of a plurality of laminated insulating layers and having a mounting portion for mounting a semiconductor element, in the center of a top surface thereof; a ground bonding pad and a power-supply bonding pad formed on the top surface of the insulating substrate, at the periphery of the semiconductor element-mounting portion, to which a ground electrode and a power-supply electrode of the semiconductor element are connected; and a pair of capacitor-connecting pads, formed on the underside of the insulating substrate, one of which is connected to the ground bonding pad, the other of which is connected to the power-supply bonding pad, and to both of which electrodes of a chip capacitor are connected, characterized by having a ground plane and a power-supply plane sandwiching at least one of the insulating layers buried opposing each other within the insulating substrate, and having electrical connections from the ground plane and the power-supply plane to the ground bonding pad and the power-supply bonding pad, respectively, at the periphery of the semiconductor element-mounting portion of the insulating substrate, to thereby downsize the package and to produce a satisfactory, noise-reducing effect.

Growing community of inventors

Kokubu, Japan

Masanao Kabumoto